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| author | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2019-09-20 15:19:20 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2019-09-20 15:19:20 +0000 |
| commit | 2b5d7e93dd18c13d5358f602d361273ec0960b37 (patch) | |
| tree | a15824af839d2677ecbf8f477ec6d473a22633c2 /llvm/test/CodeGen/Hexagon | |
| parent | d21087af958656e3eab173fc69bf7a83a3956e90 (diff) | |
| download | bcm5719-llvm-2b5d7e93dd18c13d5358f602d361273ec0960b37.tar.gz bcm5719-llvm-2b5d7e93dd18c13d5358f602d361273ec0960b37.zip | |
[MVT] Add v256i1 to MachineValueType
This type can show up when lowering some HVX vector code on Hexagon.
llvm-svn: 372403
Diffstat (limited to 'llvm/test/CodeGen/Hexagon')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll new file mode 100644 index 00000000000..b0fbb1ceaf0 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check that this doesn't crash. The select should be broken up into two +; vmux instructions. + +; CHECK-LABEL: foo: +; CHECK: vmux +; CHECK: vmux +define <256 x i8> @foo(<256 x i8> %a0, <256 x i8> %a1) #0 { + %v0 = icmp slt <256 x i8> %a0, zeroinitializer + %v1 = select <256 x i1> %v0, <256 x i8> %a1, <256 x i8> %a0 + ret <256 x i8> %v1 +} + +attributes #0 = { "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length128b" } |
