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| author | Craig Topper <craig.topper@intel.com> | 2018-03-18 03:24:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-18 03:24:42 +0000 |
| commit | 89dcda3e90df1a6a045daa69c7adfa6c13090721 (patch) | |
| tree | 0090c3083253d61e1047c03f943912280f130def /llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll | |
| parent | 52b5bf8ba9d476f5674aa6e7db714c8787ef9c65 (diff) | |
| download | bcm5719-llvm-89dcda3e90df1a6a045daa69c7adfa6c13090721.tar.gz bcm5719-llvm-89dcda3e90df1a6a045daa69c7adfa6c13090721.zip | |
[X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.
The information was so wildly inaccurate and incomplete its better to just remove it.
MMX_MASKMOVQ64 showed up twice in several scheduler models. In Haswell and Broadwell they were on adjacent lines. On Skylake the copies had different information.
MMX_MASKMOVQ and MASKMOVDQU were completely missing.
MMX_MASKMOVQ64 was listed on Haswell/Broadwell as 1 cycle on port 1 despite it being a store instruction.
Filed PR36780 to track fixing this right.
llvm-svn: 327783
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll')
0 files changed, 0 insertions, 0 deletions
