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authorSumanth Gundapaneni <sgundapa@codeaurora.org>2017-10-18 18:07:07 +0000
committerSumanth Gundapaneni <sgundapa@codeaurora.org>2017-10-18 18:07:07 +0000
commite1983bcf552980433a7a8ed7a2ae31ded4ae9b4a (patch)
treea971d5be4ebd3445c32d5c802eac212ce2843964 /llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
parent265d253aae7b6d44618e07db7ee042b4b1aeb9c6 (diff)
downloadbcm5719-llvm-e1983bcf552980433a7a8ed7a2ae31ded4ae9b4a.tar.gz
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[Hexagon] New HVX target features.
This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll')
-rw-r--r--llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
index ae09062638d..2661f8c0d0d 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
@@ -24,7 +24,7 @@ if.end: ; preds = %if.then, %entry
ret i32 %retval1.0
}
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
!1 = !{i32 155}
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