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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-12-11 18:57:54 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-12-11 18:57:54 +0000 |
commit | a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e (patch) | |
tree | e5c4b89bd21c115664b1be7bb84fa2ea11f8b3bd /llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll | |
parent | e83876e31d9da26c9e0c11cf7463e4a645e96bc4 (diff) | |
download | bcm5719-llvm-a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e.tar.gz bcm5719-llvm-a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e.zip |
[Hexagon] Add support for Hexagon V65
llvm-svn: 320404
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll')
-rw-r--r-- | llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll new file mode 100644 index 00000000000..405211c5dfa --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll @@ -0,0 +1,78 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s + +; CHECK-LABEL: V6_vscattermw +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermh +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermw_add +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermh_add +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermwq +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhq +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhw +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhw_add +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhwq +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}} + + +declare void @llvm.hexagon.V6.vscattermw(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermw(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermw(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermh(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermh(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermh(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermw.add(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermw_add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermw.add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermh.add(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermh_add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermh.add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermwq(<512 x i1>, i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermwq(<16 x i32> %a, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %a to <512 x i1> + call void @llvm.hexagon.V6.vscattermwq(<512 x i1> %1, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhq(<512 x i1>, i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermhq(<16 x i32> %a, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %a to <512 x i1> + call void @llvm.hexagon.V6.vscattermhq(<512 x i1> %1, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhw(i32, i32, <32 x i32>, <16 x i32>) +define void @V6_vscattermhw(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermhw(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhw.add(i32, i32, <32 x i32>, <16 x i32>) +define void @V6_vscattermhw_add(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermhw.add(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhwq(<512 x i1>, i32, i32, <32 x i32>, <16 x i32>) +define void @V6_vscattermhwq(<16 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %a to <512 x i1> + call void @llvm.hexagon.V6.vscattermhwq(<512 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <16 x i32> %e) + ret void +} |