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| author | Sanjay Patel <spatel@rotateright.com> | 2018-05-16 22:49:08 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-05-16 22:49:08 +0000 |
| commit | ae83159530f2657d35bc2543065e23256489d7ea (patch) | |
| tree | 9b362b34ac369bf001c10e8f8255ac4644f33a2e /llvm/test/CodeGen/Hexagon/fp_latency.ll | |
| parent | 354842abc5b432407dba547c0351609c31b32f43 (diff) | |
| download | bcm5719-llvm-ae83159530f2657d35bc2543065e23256489d7ea.tar.gz bcm5719-llvm-ae83159530f2657d35bc2543065e23256489d7ea.zip | |
[Hexagon] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
llvm-svn: 332550
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/fp_latency.ll')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/fp_latency.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/Hexagon/fp_latency.ll b/llvm/test/CodeGen/Hexagon/fp_latency.ll index 3ea14191feb..4934897a7e3 100644 --- a/llvm/test/CodeGen/Hexagon/fp_latency.ll +++ b/llvm/test/CodeGen/Hexagon/fp_latency.ll @@ -40,15 +40,15 @@ b2: ; preds = %b2, %b1 %v15 = add nsw i32 %v14, %v11 %v16 = getelementptr inbounds [1000 x float], [1000 x float]* %v1, i32 0, i32 %v15 %v17 = load float, float* %v16, align 4, !tbaa !0 - %v18 = fmul float %v17, undef + %v18 = fmul float %v17, %v17 %v19 = mul nsw i32 %v13, 25 %v20 = add nsw i32 %v19, %v11 %v21 = getelementptr inbounds [1000 x float], [1000 x float]* %v2, i32 0, i32 %v20 %v22 = load float, float* %v21, align 4, !tbaa !0 - %v23 = fmul float %v22, undef + %v23 = fmul float %v22, %v22 %v24 = fadd float %v18, %v23 %v25 = load float, float* %v12, align 4, !tbaa !0 - %v26 = fmul float %v25, undef + %v26 = fmul float %v25, %v25 %v27 = fadd float %v24, %v26 %v28 = getelementptr inbounds [1000 x float], [1000 x float]* %v0, i32 0, i32 %v20 %v29 = load float, float* %v28, align 4, !tbaa !0 |
