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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-08-02 22:17:53 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-08-02 22:17:53 +0000 |
commit | d91a9e27a987fa3e314c6d536b767e50195bb5a8 (patch) | |
tree | a43e4f748b43765de08759eee0f22827c688d4fb /llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll | |
parent | f0a57378aa2f16a9f4c9517f761ce35f78ee062f (diff) | |
download | bcm5719-llvm-d91a9e27a987fa3e314c6d536b767e50195bb5a8.tar.gz bcm5719-llvm-d91a9e27a987fa3e314c6d536b767e50195bb5a8.zip |
[Hexagon] Simplify CFG after atomic expansion
This will remove suboptimal branching from the generated ll/sc loops.
The extra simplification pass affects a lot of testcases, which have
been modified to accommodate this change: either by modifying the
test to become immune to the CFG simplification, or (less preferablt)
by adding option -hexagon-initial-cfg-clenaup=0.
llvm-svn: 338774
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll')
-rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll index 3cc73750164..67d8e6663cb 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll @@ -7,13 +7,13 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" -define void @fred() #0 { +define void @fred(i32* %a0, i32* %a1, i8* %a2) #0 { b0: - %v1 = load i32, i32* undef, align 4 + %v1 = load i32, i32* %a0, align 4 %v2 = mul nsw i32 %v1, -15137 %v3 = add nsw i32 0, %v2 %v4 = sub nsw i32 0, %v3 - %v5 = load i32, i32* undef, align 4 + %v5 = load i32, i32* %a1, align 4 %v6 = insertelement <2 x i32> undef, i32 %v5, i32 1 %v7 = add nsw <2 x i32> undef, %v6 %v8 = extractelement <2 x i32> %v7, i32 0 @@ -28,8 +28,8 @@ b0: %v17 = extractelement <8 x i32> %v16, i32 5 %v18 = getelementptr inbounds i8, i8* null, i32 %v17 %v19 = load i8, i8* %v18, align 1 - store i8 %v19, i8* undef, align 1 - unreachable + store i8 %v19, i8* %a2, align 1 + ret void } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } |