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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-03-09 16:29:30 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-03-09 16:29:30 +0000 |
| commit | 78c4fcf12eaa4fe33dd16a876becbb388e49eba3 (patch) | |
| tree | 0fd18c74ba117858cd75fb51da0af62ee6bc7175 /llvm/test/CodeGen/Hexagon/adde.ll | |
| parent | 2b1f6f4b92b28278f38812e4497aa115b904b161 (diff) | |
| download | bcm5719-llvm-78c4fcf12eaa4fe33dd16a876becbb388e49eba3.tar.gz bcm5719-llvm-78c4fcf12eaa4fe33dd16a876becbb388e49eba3.zip | |
[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
(op ... (zext i1 c) ...) -> (select c (op ... 1 ...),
(op ... 0 ...))
llvm-svn: 297391
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/adde.ll')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/adde.ll | 54 |
1 files changed, 24 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/Hexagon/adde.ll b/llvm/test/CodeGen/Hexagon/adde.ll index 5af3b071cd0..12913eea7e8 100644 --- a/llvm/test/CodeGen/Hexagon/adde.ll +++ b/llvm/test/CodeGen/Hexagon/adde.ll @@ -1,33 +1,27 @@ -; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s +; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s -; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1) -; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) -; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},#1,#0) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK-DAG: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK-DAG: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK-DAG: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK-DAG: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK-DAG: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK-DAG: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) - -define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { -entry: - %tmp1 = zext i64 %AL to i128 - %tmp23 = zext i64 %AH to i128 - %tmp4 = shl i128 %tmp23, 64 - %tmp5 = or i128 %tmp4, %tmp1 - %tmp67 = zext i64 %BL to i128 - %tmp89 = zext i64 %BH to i128 - %tmp11 = shl i128 %tmp89, 64 - %tmp12 = or i128 %tmp11, %tmp67 - %tmp15 = add i128 %tmp12, %tmp5 - %tmp1617 = trunc i128 %tmp15 to i64 - store i64 %tmp1617, i64* %RL - %tmp21 = lshr i128 %tmp15, 64 - %tmp2122 = trunc i128 %tmp21 to i64 - store i64 %tmp2122, i64* %RH - ret void +define void @check_adde_addc(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64* %a4, i64* %a5) { +b6: + %v7 = zext i64 %a0 to i128 + %v8 = zext i64 %a1 to i128 + %v9 = shl i128 %v8, 64 + %v10 = or i128 %v7, %v9 + %v11 = zext i64 %a2 to i128 + %v12 = zext i64 %a3 to i128 + %v13 = shl i128 %v12, 64 + %v14 = or i128 %v11, %v13 + %v15 = add i128 %v10, %v14 + %v16 = lshr i128 %v15, 64 + %v17 = trunc i128 %v15 to i64 + %v18 = trunc i128 %v16 to i64 + store i64 %v17, i64* %a4 + store i64 %v18, i64* %a5 + ret void } |
