[CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2

Summary:
For below test case, we will get assert error except for AArch64 and ARM:

declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
define i8 @test_v3i8(<3 x i8> %a) nounwind {
  %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
  ret i8 %b
}
In the function getShuffleReduction (), we can see it needs the vector size must be power of 2.

This patch is fix below error when the number of element is not power of 2 for those llvm.experimental.vector.reduce.* function.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D68625

1 files changed, 13 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
index a13c23d2e59..11abf902eeb 100644
--- a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
+++ b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
@@ -18,6 +18,7 @@ declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
 declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
 declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
 
+declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8>)
 
 define i64 @add_i64(<2 x i64> %vec) {
 ; CHECK-LABEL: @add_i64(
@@ -303,3 +304,15 @@ entry:
   %r = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %vec)
   ret double %r
 }
+
+; Test when the vector size is not power of two.
+define i8 @test_v3i8(<3 x i8> %a) nounwind {
+; CHECK-LABEL: @test_v3i8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    %b = call i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a)
+; CHECK-NEXT:    ret i8 %b
+;
+entry:
+  %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
+  ret i8 %b
+}