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author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
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committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll | |
parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll')
-rw-r--r-- | llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll b/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll index 5aa827a0ab8..be1e0a39b3b 100644 --- a/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll +++ b/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll @@ -8,13 +8,13 @@ entry: %rv = alloca i32, align 4 store i8* %p, i8** %p.addr, align 8 store i32 0, i32* @G, align 4 - %0 = load i8** %p.addr, align 8 + %0 = load i8*, i8** %p.addr, align 8 ; CHECK: blah %1 = call i32 asm "blah", "=r,r,~{memory}"(i8* %0) nounwind ; CHECK: @G store i32 %1, i32* %rv, align 4 - %2 = load i32* %rv, align 4 - %3 = load i32* @G, align 4 + %2 = load i32, i32* %rv, align 4 + %3 = load i32, i32* @G, align 4 %add = add nsw i32 %2, %3 ret i32 %add } |