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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-09-16 12:29:33 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-09-16 12:29:33 +0000 |
| commit | c0e9b8d8bb325d91c53b0656d39cf959bbc49fb7 (patch) | |
| tree | 42eac12e2ca53dc0192ac976b6bf01a0e89ab4e8 /llvm/test/CodeGen/CellSPU/v2i32.ll | |
| parent | 84a3bddfc364913a38b44cd6447f9200763047d6 (diff) | |
| download | bcm5719-llvm-c0e9b8d8bb325d91c53b0656d39cf959bbc49fb7.tar.gz bcm5719-llvm-c0e9b8d8bb325d91c53b0656d39cf959bbc49fb7.zip | |
Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
llvm-svn: 114074
Diffstat (limited to 'llvm/test/CodeGen/CellSPU/v2i32.ll')
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/v2i32.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/CellSPU/v2i32.ll b/llvm/test/CodeGen/CellSPU/v2i32.ll index dd51be5a71d..8cfc490e02d 100644 --- a/llvm/test/CodeGen/CellSPU/v2i32.ll +++ b/llvm/test/CodeGen/CellSPU/v2i32.ll @@ -37,9 +37,8 @@ define %vec @test_mul(%vec %param) } define <2 x i32> @test_splat(i32 %param ) { -;TODO insertelement transforms to a PREFSLOT2VEC, that trasforms to the -; somewhat redundant: -;CHECK-NOT or $3, $3, $3 +;see svn log for why this is here... +;CHECK-NOT: or $3, $3, $3 ;CHECK: lqa ;CHECK: shufb %sv = insertelement <1 x i32> undef, i32 %param, i32 0 |
