More CellSPU refinement and progress:

- Cleaned up custom load/store logic, common code is now shared [see note
  below], cleaned up address modes

- More test cases: various intrinsics, structure element access (load/store
  test), updated target data strings, indirect function calls.

Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode
structures: they now share a common base class, LSBaseSDNode, that
provides an interface to their common functionality. There is some hackery
to access the proper operand depending on the derived class; otherwise,
to do a proper job would require finding and rearranging the SDOperands
sent to StoreSDNode's constructor. The current refactor errs on the
side of being conservatively and backwardly compatible while providing
functionality that reduces redundant code for targets where loads and
stores are custom-lowered.

llvm-svn: 45851

1 files changed, 2 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/CellSPU/or_ops.ll b/llvm/test/CodeGen/CellSPU/or_ops.ll
index 6c46b413871..91e3e2145ab 100644
--- a/llvm/test/CodeGen/CellSPU/or_ops.ll
+++ b/llvm/test/CodeGen/CellSPU/or_ops.ll
@@ -4,6 +4,8 @@
 ; RUN: grep ori    %t1.s | count 30
 ; RUN: grep orhi   %t1.s | count 30
 ; RUN: grep orbi   %t1.s | count 15
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
 
 ; OR instruction generation:
 define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {