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authorKalle Raiskila <kalle.raiskila@nokia.com>2010-06-21 15:08:16 +0000
committerKalle Raiskila <kalle.raiskila@nokia.com>2010-06-21 15:08:16 +0000
commit0ab5a02579db6fa3a72f6bf11725f91efd71b498 (patch)
tree106bb60a600fc6c709561f2a87283e6869ca46cc /llvm/test/CodeGen/CellSPU/call_indirect.ll
parentd7f50c118ab3e16de75dd49559dc431ce46c48a5 (diff)
downloadbcm5719-llvm-0ab5a02579db6fa3a72f6bf11725f91efd71b498.tar.gz
bcm5719-llvm-0ab5a02579db6fa3a72f6bf11725f91efd71b498.zip
Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. llvm-svn: 106420
Diffstat (limited to 'llvm/test/CodeGen/CellSPU/call_indirect.ll')
-rw-r--r--llvm/test/CodeGen/CellSPU/call_indirect.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/CellSPU/call_indirect.ll b/llvm/test/CodeGen/CellSPU/call_indirect.ll
index 08dad74843e..d94d77c9f14 100644
--- a/llvm/test/CodeGen/CellSPU/call_indirect.ll
+++ b/llvm/test/CodeGen/CellSPU/call_indirect.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=cellspu -asm-verbose=0 > %t1.s
-; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 > %t2.s
+; RUN: llc < %s -march=cellspu -asm-verbose=0 -regalloc=linearscan > %t1.s
+; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 -regalloc=linearscan > %t2.s
; RUN: grep bisl %t1.s | count 7
; RUN: grep ila %t1.s | count 1
; RUN: grep rotqby %t1.s | count 5
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