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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-21 15:08:16 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-21 15:08:16 +0000 |
| commit | 0ab5a02579db6fa3a72f6bf11725f91efd71b498 (patch) | |
| tree | 106bb60a600fc6c709561f2a87283e6869ca46cc /llvm/test/CodeGen/CellSPU/call.ll | |
| parent | d7f50c118ab3e16de75dd49559dc431ce46c48a5 (diff) | |
| download | bcm5719-llvm-0ab5a02579db6fa3a72f6bf11725f91efd71b498.tar.gz bcm5719-llvm-0ab5a02579db6fa3a72f6bf11725f91efd71b498.zip | |
Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
llvm-svn: 106420
Diffstat (limited to 'llvm/test/CodeGen/CellSPU/call.ll')
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/call.ll | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/CellSPU/call.ll b/llvm/test/CodeGen/CellSPU/call.ll index 960d2feaded..eb7cf2c6467 100644 --- a/llvm/test/CodeGen/CellSPU/call.ll +++ b/llvm/test/CodeGen/CellSPU/call.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=cellspu > %t1.s +; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s ; RUN: grep brsl %t1.s | count 1 ; RUN: grep brasl %t1.s | count 1 ; RUN: grep stqd %t1.s | count 80 +; RUN: llc < %s -march=cellspu | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -16,6 +17,8 @@ entry: declare void @extern_stub_1(i32, i32) define i32 @stub_1(i32 %x, float %y) { + ; CHECK: il $3, 0 + ; CHECK: bi $lr entry: ret i32 0 } |
