diff options
| author | Dan Gohman <gohman@apple.com> | 2009-06-04 22:49:04 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-06-04 22:49:04 +0000 |
| commit | a5b9645c4b7a1d8be5e41081b99f27b49b8aa8cf (patch) | |
| tree | 7f5a9f6633be0c4e77a1bb00e5bfcfcca14e219b /llvm/test/CodeGen/CBackend | |
| parent | 72a4d2fec138ad6d2becbc69c6d034246a056d09 (diff) | |
| download | bcm5719-llvm-a5b9645c4b7a1d8be5e41081b99f27b49b8aa8cf.tar.gz bcm5719-llvm-a5b9645c4b7a1d8be5e41081b99f27b49b8aa8cf.zip | |
Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
llvm-svn: 72897
Diffstat (limited to 'llvm/test/CodeGen/CBackend')
| -rw-r--r-- | llvm/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/CBackend/vectors.ll | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll b/llvm/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll index ca4e48eb5ea..f8393a3fbc8 100644 --- a/llvm/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll +++ b/llvm/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll @@ -23,7 +23,7 @@ define double @test4(i64 %L) { define double @test5(double %D) { %X = bitcast double %D to double ; <double> [#uses=1] - %Y = add double %X, 2.000000e+00 ; <double> [#uses=1] + %Y = fadd double %X, 2.000000e+00 ; <double> [#uses=1] %Z = bitcast double %Y to i64 ; <i64> [#uses=1] %res = bitcast i64 %Z to double ; <double> [#uses=1] ret double %res @@ -31,7 +31,7 @@ define double @test5(double %D) { define float @test6(float %F) { %X = bitcast float %F to float ; <float> [#uses=1] - %Y = add float %X, 2.000000e+00 ; <float> [#uses=1] + %Y = fadd float %X, 2.000000e+00 ; <float> [#uses=1] %Z = bitcast float %Y to i32 ; <i32> [#uses=1] %res = bitcast i32 %Z to float ; <float> [#uses=1] ret float %res diff --git a/llvm/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll b/llvm/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll index afcac99a76d..32d635ad720 100644 --- a/llvm/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll +++ b/llvm/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll @@ -20,7 +20,7 @@ entry: br label %bb4 bb4: ; preds = %bb5.split, %bb4, %entry - %0 = fcmp ogt ppc_fp128 0xM00000000000000000000000000000000, select (i1 fcmp olt (ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128), ppc_fp128 mul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000)), ppc_fp128 mul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000), ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128)) ; <i1> [#uses=1] + %0 = fcmp ogt ppc_fp128 0xM00000000000000000000000000000000, select (i1 fcmp olt (ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128), ppc_fp128 fmul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000)), ppc_fp128 fmul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000), ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128)) ; <i1> [#uses=1] br i1 %0, label %bb4, label %bb5.split bb5.split: ; preds = %bb4 diff --git a/llvm/test/CodeGen/CBackend/vectors.ll b/llvm/test/CodeGen/CBackend/vectors.ll index de78975491e..d01e99288f7 100644 --- a/llvm/test/CodeGen/CBackend/vectors.ll +++ b/llvm/test/CodeGen/CBackend/vectors.ll @@ -14,7 +14,7 @@ define i32 @test2(<4 x i32> %a, i32 %b) { } define <4 x float> @test3(<4 x float> %Y) { - %Z = add <4 x float> %Y, %Y + %Z = fadd <4 x float> %Y, %Y %X = shufflevector <4 x float> zeroinitializer, <4 x float> %Z, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ret <4 x float> %X } |
