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| author | Reid Spencer <rspencer@reidspencer.com> | 2007-01-17 07:59:14 +0000 |
|---|---|---|
| committer | Reid Spencer <rspencer@reidspencer.com> | 2007-01-17 07:59:14 +0000 |
| commit | 83b3d8267225d585678d5d3af9bba5735f4b415d (patch) | |
| tree | 9d6c2ad7bfd568186e83a39e6f03e1c0bf415715 /llvm/test/CodeGen/Alpha/add.ll | |
| parent | 100602d7561ca5e245db6194bddae86357d203d4 (diff) | |
| download | bcm5719-llvm-83b3d8267225d585678d5d3af9bba5735f4b415d.tar.gz bcm5719-llvm-83b3d8267225d585678d5d3af9bba5735f4b415d.zip | |
Regression is gone, don't try to find it on clean target.
llvm-svn: 33296
Diffstat (limited to 'llvm/test/CodeGen/Alpha/add.ll')
| -rw-r--r-- | llvm/test/CodeGen/Alpha/add.ll | 180 |
1 files changed, 180 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Alpha/add.ll b/llvm/test/CodeGen/Alpha/add.ll new file mode 100644 index 00000000000..e385dee2196 --- /dev/null +++ b/llvm/test/CodeGen/Alpha/add.ll @@ -0,0 +1,180 @@ +;test all the shifted and signextending adds and subs with and without consts +; +; RUN: llvm-as < %s | llc -march=alpha -o %t.s -f && +; RUN: grep ' addl' %t.s | wc -l | grep 2 && +; RUN: grep ' addq' %t.s | wc -l | grep 2 && +; RUN: grep ' subl' %t.s | wc -l | grep 2 && +; RUN: grep ' subq' %t.s | wc -l | grep 1 && +; +; RUN: grep 'lda $0,-100($16)' %t.s | wc -l | grep 1 && +; RUN: grep 's4addl' %t.s | wc -l | grep 2 && +; RUN: grep 's8addl' %t.s | wc -l | grep 2 && +; RUN: grep 's4addq' %t.s | wc -l | grep 2 && +; RUN: grep 's8addq' %t.s | wc -l | grep 2 && +; +; RUN: grep 's4subl' %t.s | wc -l | grep 2 && +; RUN: grep 's8subl' %t.s | wc -l | grep 2 && +; RUN: grep 's4subq' %t.s | wc -l | grep 2 && +; RUN: grep 's8subq' %t.s | wc -l | grep 2 + +implementation ; Functions: + +define i32 %al(i32 sext %x.s, i32 sext %y.s) sext { +entry: + %tmp.3.s = add i32 %y.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 %ali(i32 sext %x.s) sext { +entry: + %tmp.3.s = add i32 100, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 %aq(i64 sext %x.s, i64 sext %y.s) sext { +entry: + %tmp.3.s = add i64 %y.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 %aqi(i64 %x.s) { +entry: + %tmp.3.s = add i64 100, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 %sl(i32 sext %x.s, i32 sext %y.s) sext { +entry: + %tmp.3.s = sub i32 %y.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 %sli(i32 sext %x.s) sext { +entry: + %tmp.3.s = sub i32 %x.s, 100 ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 %sq(i64 %x.s, i64 %y.s) { +entry: + %tmp.3.s = sub i64 %y.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 %sqi(i64 %x.s) { +entry: + %tmp.3.s = sub i64 %x.s, 100 ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 %a4l(i32 sext %x.s, i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 2 ; <i32> [#uses=1] + %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 %a8l(i32 sext %x.s, i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 3 ; <i32> [#uses=1] + %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 %a4q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 2 ; <i64> [#uses=1] + %tmp.3.s = add i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 %a8q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 3 ; <i64> [#uses=1] + %tmp.3.s = add i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 %a4li(i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 2 ; <i32> [#uses=1] + %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 %a8li(i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 3 ; <i32> [#uses=1] + %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 %a4qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 2 ; <i64> [#uses=1] + %tmp.3.s = add i64 100, %tmp.1.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 %a8qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 3 ; <i64> [#uses=1] + %tmp.3.s = add i64 100, %tmp.1.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 %s4l(i32 sext %x.s, i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 2 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 %s8l(i32 sext %x.s, i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 3 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 %s4q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 2 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 %s8q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 3 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 %s4li(i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 2 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 %s8li(i32 sext %y.s) sext { +entry: + %tmp.1.s = shl i32 %y.s, i8 3 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 %s4qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 2 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, 100 ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 %s8qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, i8 3 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, 100 ; <i64> [#uses=1] + ret i64 %tmp.3.s +} |

