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| author | Dylan McKay <me@dylanmckay.io> | 2018-09-01 12:22:07 +0000 |
|---|---|---|
| committer | Dylan McKay <me@dylanmckay.io> | 2018-09-01 12:22:07 +0000 |
| commit | 8b0f9d2e58f1cb0267ebed9eec3de6b54ba10a98 (patch) | |
| tree | 6fbea5137c0dfdb6cc96ec9d0af18e85d748cc0f /llvm/test/CodeGen/AVR | |
| parent | 89d2245a2ac5d6690166d0752da49d011fff9a7d (diff) | |
| download | bcm5719-llvm-8b0f9d2e58f1cb0267ebed9eec3de6b54ba10a98.tar.gz bcm5719-llvm-8b0f9d2e58f1cb0267ebed9eec3de6b54ba10a98.zip | |
[AVR] Define the ROL instruction as an alias of ADC
The 'rol Rd' instruction is equivalent to 'adc Rd'.
This caused compile warnings from tablegen because of conflicting bits
shared between each instruction.
llvm-svn: 341275
Diffstat (limited to 'llvm/test/CodeGen/AVR')
| -rw-r--r-- | llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir index 5eccebbb477..854b350d98b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir @@ -16,7 +16,7 @@ body: | ; CHECK-LABEL: test ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg - ; CHECK-NEXT: $r15 = ROLRd $r15, implicit-def $sreg, implicit killed $sreg + ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg $r15r14 = LSLWRd $r15r14, implicit-def $sreg ... |
