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| author | Chad Rosier <mcrosier@codeaurora.org> | 2014-05-19 22:59:51 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-05-19 22:59:51 +0000 |
| commit | b06ed63ebf65c9c1d900724ffbacd6dc99e03363 (patch) | |
| tree | 52c16363ed02fe3092fcc132edbe4150ac209bb6 /llvm/test/CodeGen/ARM64 | |
| parent | 97b084f52859cc07b1e8c28357dac7f5bbb00dd0 (diff) | |
| download | bcm5719-llvm-b06ed63ebf65c9c1d900724ffbacd6dc99e03363.tar.gz bcm5719-llvm-b06ed63ebf65c9c1d900724ffbacd6dc99e03363.zip | |
[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.
Patch by Dave Estes<cestes@codeaurora.org>!
PR19761 http://reviews.llvm.org/D3829
llvm-svn: 209176
Diffstat (limited to 'llvm/test/CodeGen/ARM64')
| -rw-r--r-- | llvm/test/CodeGen/ARM64/misched-basic-A53.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM64/misched-basic-A53.ll b/llvm/test/CodeGen/ARM64/misched-basic-A53.ll index 608e5b65b63..b87a523a30b 100644 --- a/llvm/test/CodeGen/ARM64/misched-basic-A53.ll +++ b/llvm/test/CodeGen/ARM64/misched-basic-A53.ll @@ -108,3 +108,18 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } + + +; Regression Test for Bug 19761 +; - [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load +; - http://llvm.org/bugs/show_bug.cgi?id=19761 +; +; Nothing explicit to check other than llc not crashing. +define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) { + %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A) + %tmp = getelementptr i8* %A, i32 32 + store i8* %tmp, i8** %ptr + ret { <16 x i8>, <16 x i8> } %ld2 +} + +declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8*) |
