ARM64: fix SELECT_CC lowering in absence of NaNs.

We were swapping the true & false results while testing for FMAX/FMIN,
but not putting them back to the original state if the later checks
failed.

Should fix PR19700.

llvm-svn: 208469

1 files changed, 15 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/ARM64/fmax.ll b/llvm/test/CodeGen/ARM64/fmax.ll
index 53ecf86a022..94b745437bd 100644
--- a/llvm/test/CodeGen/ARM64/fmax.ll
+++ b/llvm/test/CodeGen/ARM64/fmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=arm64 -enable-no-nans-fp-math < %s | FileCheck %s
 
 define double @test_direct(float %in) #1 {
-entry:
+; CHECK-LABEL: test_direct:
   %cmp = fcmp olt float %in, 0.000000e+00
   %longer = fpext float %in to double
   %val = select i1 %cmp, double 0.000000e+00, double %longer
@@ -11,7 +11,7 @@ entry:
 }
 
 define double @test_cross(float %in) #1 {
-entry:
+; CHECK-LABEL: test_cross:
   %cmp = fcmp olt float %in, 0.000000e+00
   %longer = fpext float %in to double
   %val = select i1 %cmp, double %longer, double 0.000000e+00
@@ -19,3 +19,16 @@ entry:
 
 ; CHECK: fmin
 }
+
+; This isn't a min or a max, but passes the first condition for swapping the
+; results. Make sure they're put back before we resort to the normal fcsel.
+define float @test_cross_fail(float %lhs, float %rhs) {
+; CHECK-LABEL: test_cross_fail:
+  %tst = fcmp une float %lhs, %rhs
+  %res = select i1 %tst, float %rhs, float %lhs
+  ret float %res
+
+  ; The register allocator would have to decide to be deliberately obtuse before
+  ; other register were used.
+; CHECK: fcsel s0, s1, s0, ne
+}
\ No newline at end of file