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| author | Jim Grosbach <grosbach@apple.com> | 2014-04-17 20:47:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2014-04-17 20:47:31 +0000 |
| commit | 0fba6d98fcb0438f1fc4f0c67e989f49843762ec (patch) | |
| tree | fe3f261810f1755fc830e8cc945b5219e0dd5cc2 /llvm/test/CodeGen/ARM64/aapcs.ll | |
| parent | 4b600d3f0b923b5f8c1d39bb944e12e370c10013 (diff) | |
| download | bcm5719-llvm-0fba6d98fcb0438f1fc4f0c67e989f49843762ec.tar.gz bcm5719-llvm-0fba6d98fcb0438f1fc4f0c67e989f49843762ec.zip | |
ARM64: [su]xtw use W regs as inputs, not X regs.
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.
PR19455 and rdar://16650642
llvm-svn: 206495
Diffstat (limited to 'llvm/test/CodeGen/ARM64/aapcs.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM64/aapcs.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM64/aapcs.ll b/llvm/test/CodeGen/ARM64/aapcs.ll index e4889b77166..3998aaad2de 100644 --- a/llvm/test/CodeGen/ARM64/aapcs.ll +++ b/llvm/test/CodeGen/ARM64/aapcs.ll @@ -57,7 +57,7 @@ define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) { %ext_char = sext i8 %char to i64 store volatile i64 %ext_char, i64* @var64 -; CHECK: sxtb [[EXT:x[0-9]+]], x1 +; CHECK: sxtb [[EXT:x[0-9]+]], w1 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] %ext_short = zext i16 %short to i64 @@ -67,7 +67,7 @@ define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) { %ext_int = zext i32 %int to i64 store volatile i64 %ext_int, i64* @var64 -; CHECK: uxtw [[EXT:x[0-9]+]], x3 +; CHECK: uxtw [[EXT:x[0-9]+]], w3 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] ret void |
