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| author | Silviu Baranga <silviu.baranga@arm.com> | 2015-08-19 14:11:27 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2015-08-19 14:11:27 +0000 |
| commit | ad1b19fcb718b1010aaab492e3cab80ab7a71406 (patch) | |
| tree | f466116dfcd807a04d103d33fdc70e70afc1819e /llvm/test/CodeGen/ARM/vselect_imax.ll | |
| parent | 746da5fe2a407254753965473728ee574d1b906c (diff) | |
| download | bcm5719-llvm-ad1b19fcb718b1010aaab492e3cab80ab7a71406.tar.gz bcm5719-llvm-ad1b19fcb718b1010aaab492e3cab80ab7a71406.zip | |
[ARM] Add instruction selection patterns for vmin/vmax
Summary:
The mid-end was generating vector smin/smax/umin/umax nodes, but
we were using vbsl to generatate the code. This adds the vmin/vmax
patterns and a test to check that we are now generating vmin/vmax
instructions.
Reviewers: rengolin, jmolloy
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D12105
llvm-svn: 245439
Diffstat (limited to 'llvm/test/CodeGen/ARM/vselect_imax.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vselect_imax.ll | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/ARM/vselect_imax.ll b/llvm/test/CodeGen/ARM/vselect_imax.ll index 0eb051036d9..3f52ac2db87 100644 --- a/llvm/test/CodeGen/ARM/vselect_imax.ll +++ b/llvm/test/CodeGen/ARM/vselect_imax.ll @@ -3,8 +3,7 @@ ; Make sure that ARM backend with NEON handles vselect. define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { -; CHECK: vcgt.s32 [[QR:q[0-9]+]], [[Q1:q[0-9]+]], [[Q2:q[0-9]+]] -; CHECK: vbsl [[QR]], [[Q1]], [[Q2]] +; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} %cmpres = icmp sgt <4 x i32> %a, %b %maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b store <4 x i32> %maxres, <4 x i32>* %m @@ -21,8 +20,8 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, %v0 = load %T0_10, %T0_10* %loadaddr %v1 = load %T0_10, %T0_10* %loadaddr2 %c = icmp slt %T0_10 %v0, %v1 -; CHECK: vbsl -; CHECK: vbsl +; CHECK: vmin.s16 +; CHECK: vmin.s16 ; COST: func_blend10 ; COST: cost of 40 {{.*}} select %r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1 @@ -37,8 +36,8 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, %v0 = load %T0_14, %T0_14* %loadaddr %v1 = load %T0_14, %T0_14* %loadaddr2 %c = icmp slt %T0_14 %v0, %v1 -; CHECK: vbsl -; CHECK: vbsl +; CHECK: vmin.s32 +; CHECK: vmin.s32 ; COST: func_blend14 ; COST: cost of 41 {{.*}} select %r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1 @@ -50,8 +49,8 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, ; CHECK-LABEL: func_blend15: define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2, %T1_15* %blend, %T0_15* %storeaddr) { -; CHECK: vbsl -; CHECK: vbsl +; CHECK: vmin.s32 +; CHECK: vmin.s32 %v0 = load %T0_15, %T0_15* %loadaddr %v1 = load %T0_15, %T0_15* %loadaddr2 %c = icmp slt %T0_15 %v0, %v1 |
