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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 20:31:33 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 20:31:33 +0000 |
| commit | 486ff59a9f3805339da20634d288b162eda0e82a (patch) | |
| tree | 8296eda8e6fdca2ffaaac6695adf1f10c628b3a8 /llvm/test/CodeGen/ARM/vrev.ll | |
| parent | 84baea77eabbba4bd8b3015d4973889649c6439a (diff) | |
| download | bcm5719-llvm-486ff59a9f3805339da20634d288b162eda0e82a.tar.gz bcm5719-llvm-486ff59a9f3805339da20634d288b162eda0e82a.zip | |
Enable element promotion type legalization by deafault.
Changed tests which assumed that vectors are legalized by widening them.
llvm-svn: 142152
Diffstat (limited to 'llvm/test/CodeGen/ARM/vrev.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vrev.ll | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/vrev.ll b/llvm/test/CodeGen/ARM/vrev.ll index 34acd1678ae..5c3c0fca10d 100644 --- a/llvm/test/CodeGen/ARM/vrev.ll +++ b/llvm/test/CodeGen/ARM/vrev.ll @@ -150,9 +150,6 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind { ; vrev <4 x i16> should use VREV32 and not VREV64 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { -; CHECK: test_vrev64: -; CHECK: vext.16 -; CHECK: vrev32.16 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* %tmp2 = load <8 x i16>* %0, align 4 |
