[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/test/CodeGen/ARM/vector-extend-narrow.ll b/llvm/test/CodeGen/ARM/vector-extend-narrow.ll
index f3218969c78..7e2751b5cf5 100644
--- a/llvm/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/llvm/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -4,7 +4,7 @@
 define float @f(<4 x i16>* nocapture %in) {
   ; CHECK: vldr
   ; CHECK: vmovl.u16
-  %1 = load <4 x i16>* %in
+  %1 = load <4 x i16>, <4 x i16>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i16> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
@@ -25,7 +25,7 @@ define float @g(<4 x i8>* nocapture %in) {
   ; CHECK: vld1
   ; CHECK: vmovl.u8
   ; CHECK: vmovl.u16
-  %1 = load <4 x i8>* %in
+  %1 = load <4 x i8>, <4 x i8>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i8> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
@@ -58,7 +58,7 @@ define <4 x i8> @i(<4 x i8>* %x) {
   ; CHECK: vrecps
   ; CHECK: vmul
   ; CHECK: vmovn
-  %1 = load <4 x i8>* %x, align 4
+  %1 = load <4 x i8>, <4 x i8>* %x, align 4
   %2 = sdiv <4 x i8> zeroinitializer, %1
   ret <4 x i8> %2
 }
@@ -68,7 +68,7 @@ define <4 x i32> @j(<4 x i8>* %in) nounwind {
   ; CHECK: vmovl.u8
   ; CHECK: vmovl.u16
   ; CHECK-NOT: vand
-  %1 = load <4 x i8>* %in, align 4
+  %1 = load <4 x i8>, <4 x i8>* %in, align 4
   %2 = zext <4 x i8> %1 to <4 x i32>
   ret <4 x i32> %2
 }