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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-09-05 08:57:21 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-09-05 08:57:21 +0000 |
| commit | 3f40d872076064b7e7dcddd2ac7711396c1cb32c (patch) | |
| tree | 83f9d5614ef4f01663a3691c09c648fc680d50a6 /llvm/test/CodeGen/ARM/vector-extend-narrow.ll | |
| parent | 1a5e423602a973b1b5fc3af0e948b692fa4c18e5 (diff) | |
| download | bcm5719-llvm-3f40d872076064b7e7dcddd2ac7711396c1cb32c.tar.gz bcm5719-llvm-3f40d872076064b7e7dcddd2ac7711396c1cb32c.zip | |
Fixed the DAG combiner to better handle the folding of AND nodes for vector types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value.
llvm-svn: 163203
Diffstat (limited to 'llvm/test/CodeGen/ARM/vector-extend-narrow.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vector-extend-narrow.ll | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/vector-extend-narrow.ll b/llvm/test/CodeGen/ARM/vector-extend-narrow.ll index 8fd3db29197..22af7976212 100644 --- a/llvm/test/CodeGen/ARM/vector-extend-narrow.ll +++ b/llvm/test/CodeGen/ARM/vector-extend-narrow.ll @@ -62,3 +62,14 @@ define <4 x i8> @i(<4 x i8>* %x) { %2 = sdiv <4 x i8> zeroinitializer, %1 ret <4 x i8> %2 } +; CHECK: j: +define <4 x i32> @j(<4 x i8>* %in) nounwind { + ; CHECK: vld1 + ; CHECK: vmovl.u8 + ; CHECK: vmovl.u16 + ; CHECK-NOT: vand + %1 = load <4 x i8>* %in, align 4 + %2 = zext <4 x i8> %1 to <4 x i32> + ret <4 x i32> %2 +} + |
