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| author | Nikita Popov <nikita.ppv@gmail.com> | 2020-01-21 21:48:07 +0100 |
|---|---|---|
| committer | Hans Wennborg <hans@chromium.org> | 2020-02-05 13:51:46 +0100 |
| commit | 0b8a540dff86662fc9426bb4dd8797c547db5000 (patch) | |
| tree | 86712859ba40431a8e9d9ee7bff24c587272951e /llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll | |
| parent | 211aa5bf59eb36cd40b38b596901b6ce7cc84ba2 (diff) | |
| download | bcm5719-llvm-0b8a540dff86662fc9426bb4dd8797c547db5000.tar.gz bcm5719-llvm-0b8a540dff86662fc9426bb4dd8797c547db5000.zip | |
[AArch64][ARM] Always expand ordered vector reductions (PR44600)
fadd/fmul reductions without reassoc are lowered to
VECREDUCE_STRICT_FADD/FMUL nodes, which don't have legalization
support. Until that is in place, expand these intrinsics on
ARM and AArch64. Other targets always expand the vector reduction
intrinsics.
Additionally expand fmax/fmin reductions without nonan flag on
AArch64, as the backend asserts that the flag is present when
lowering VECREDUCE_FMIN/FMAX.
This fixes https://bugs.llvm.org/show_bug.cgi?id=44600.
Differential Revision: https://reviews.llvm.org/D73135
(cherry picked from commit 70d345e687caba4ac1f95655c6924dfa91e0083f)
Diffstat (limited to 'llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll')
0 files changed, 0 insertions, 0 deletions
