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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-11-02 11:06:18 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-11-02 11:06:18 +0000 |
| commit | cdcbeb4997a85895266b688b6077c48fbe1c4085 (patch) | |
| tree | 438fa676cd6db4c0b6f1ca30190f431433cacd63 /llvm/test/CodeGen/ARM/vdup.ll | |
| parent | dfc56b43fadf5c4f84cdb8706f29ccf1ba68e5f1 (diff) | |
| download | bcm5719-llvm-cdcbeb4997a85895266b688b6077c48fbe1c4085.tar.gz bcm5719-llvm-cdcbeb4997a85895266b688b6077c48fbe1c4085.zip | |
[DAGCombiner] Remove reduceBuildVecConvertToConvertBuildVec and rely on the vectorizers instead (PR35732)
reduceBuildVecConvertToConvertBuildVec vectorizes int2float in the DAGCombiner, which means that even if the LV/SLP has decided to keep scalar code using the cost models, this will override this.
While there are cases where vectorization is necessary in the DAG (mainly due to legalization artefacts), I don't think this is the case here, we should assume that the vectorizers know what they are doing.
Differential Revision: https://reviews.llvm.org/D53712
llvm-svn: 345964
Diffstat (limited to 'llvm/test/CodeGen/ARM/vdup.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vdup.ll | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/llvm/test/CodeGen/ARM/vdup.ll b/llvm/test/CodeGen/ARM/vdup.ll index c16a2a9e3c0..5127dab2656 100644 --- a/llvm/test/CodeGen/ARM/vdup.ll +++ b/llvm/test/CodeGen/ARM/vdup.ll @@ -488,11 +488,12 @@ define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) { ; CHECK-LABEL: check_spr_splat2: ; CHECK: @ %bb.0: ; CHECK-NEXT: lsl r2, r2, #16 -; CHECK-NEXT: vmov d17, r0, r1 +; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: asr r2, r2, #16 -; CHECK-NEXT: vdup.32 d16, r2 -; CHECK-NEXT: vcvt.f32.s32 d16, d16 -; CHECK-NEXT: vsub.f32 d16, d16, d17 +; CHECK-NEXT: vmov s0, r2 +; CHECK-NEXT: vcvt.f32.s32 s0, s0 +; CHECK-NEXT: vdup.32 d17, d0[0] +; CHECK-NEXT: vsub.f32 d16, d17, d16 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: mov pc, lr %conv = sitofp i16 %q to float @@ -505,13 +506,13 @@ define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) { define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) { ; CHECK-LABEL: check_spr_splat4: ; CHECK: @ %bb.0: -; CHECK-NEXT: mov r12, sp -; CHECK-NEXT: vmov d19, r2, r3 -; CHECK-NEXT: vld1.16 {d16[]}, [r12:16] -; CHECK-NEXT: vmov d18, r0, r1 -; CHECK-NEXT: vmovl.s16 q8, d16 -; CHECK-NEXT: vcvt.f32.s32 q8, q8 -; CHECK-NEXT: vsub.f32 q8, q8, q9 +; CHECK-NEXT: ldrsh r12, [sp] +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vmov s0, r12 +; CHECK-NEXT: vcvt.f32.s32 s0, s0 +; CHECK-NEXT: vdup.32 q9, d0[0] +; CHECK-NEXT: vsub.f32 q8, q9, q8 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: mov pc, lr @@ -525,13 +526,13 @@ define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) { define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) { ; CHECK-LABEL: check_spr_splat4_lane1: ; CHECK: @ %bb.0: -; CHECK-NEXT: mov r12, sp -; CHECK-NEXT: vmov d19, r2, r3 -; CHECK-NEXT: vld1.16 {d16[]}, [r12:16] -; CHECK-NEXT: vmov d18, r0, r1 -; CHECK-NEXT: vmovl.s16 q8, d16 -; CHECK-NEXT: vcvt.f32.s32 q8, q8 -; CHECK-NEXT: vsub.f32 q8, q8, q9 +; CHECK-NEXT: ldrsh r12, [sp] +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vmov s0, r12 +; CHECK-NEXT: vcvt.f32.s32 s0, s0 +; CHECK-NEXT: vdup.32 q9, d0[0] +; CHECK-NEXT: vsub.f32 q8, q9, q8 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: mov pc, lr |
