diff options
| author | Robin Morisset <morisset@google.com> | 2014-09-23 23:18:01 +0000 |
|---|---|---|
| committer | Robin Morisset <morisset@google.com> | 2014-09-23 23:18:01 +0000 |
| commit | dc1b248ccff76e1891badfc1aa3f54ce6e30ae43 (patch) | |
| tree | 1db5df56ca3c91c5e79076fdca78a884824aa006 /llvm/test/CodeGen/ARM/swift-atomics.ll | |
| parent | c2e67539582f573c3aeb991eed5a17a9a80d939f (diff) | |
| download | bcm5719-llvm-dc1b248ccff76e1891badfc1aa3f54ce6e30ae43.tar.gz bcm5719-llvm-dc1b248ccff76e1891badfc1aa3f54ce6e30ae43.zip | |
Fix swift-atomics testcase
This testcase was not testing what it meant: because there were only two checks for
dmb {{ish}} in the second function, it could have missed a bug where one of the three
required dmb {{ish}} became dmb {{ishst}}. As I was fixing it, I also added
CHECK-LABELs to make it a bit less brittle.
llvm-svn: 218341
Diffstat (limited to 'llvm/test/CodeGen/ARM/swift-atomics.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/swift-atomics.ll | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/swift-atomics.ll b/llvm/test/CodeGen/ARM/swift-atomics.ll index 1d718155710..8b100f1f41f 100644 --- a/llvm/test/CodeGen/ARM/swift-atomics.ll +++ b/llvm/test/CodeGen/ARM/swift-atomics.ll @@ -8,6 +8,7 @@ define void @test_store_release(i32* %p, i32 %v) { ; CHECK: dmb ishst ; CHECK: str +; CHECK-STRICT-ATOMIC-LABEL: test_store_release: ; CHECK-STRICT-ATOMIC: dmb {{ish$}} store atomic i32 %v, i32* %p release, align 4 ret void @@ -24,7 +25,11 @@ define i32 @test_seq_cst(i32* %p, i32 %v) { ; CHECK: ldr ; CHECK: dmb {{ish$}} +; CHECK-STRICT-ATOMIC-LABEL: test_seq_cst: ; CHECK-STRICT-ATOMIC: dmb {{ish$}} +; CHECK-STRICT-ATOMIC: str +; CHECK-STRICT-ATOMIC: dmb {{ish$}} +; CHECK-STRICT-ATOMIC: ldr ; CHECK-STRICT-ATOMIC: dmb {{ish$}} store atomic i32 %v, i32* %p seq_cst, align 4 @@ -39,6 +44,7 @@ define i32 @test_acq(i32* %addr) { ; CHECK: ldr ; CHECK: dmb {{ish$}} +; CHECK-STRICT-ATOMIC-LABEL: test_acq: ; CHECK-STRICT-ATOMIC: dmb {{ish$}} %val = load atomic i32* %addr acquire, align 4 ret i32 %val |
