[Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)

Summary:
This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]].
In middle-end, we'd want to prefer the form with two adds - D63992,
but as this diff shows, not every target will prefer that pattern.

Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars,
but only X86 prefer that same pattern for vectors.

Here i'm adding a new TLI hook, always defaulting to the inc-of-add,
but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars.

Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel

Reviewed By: efriedma

Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64090

llvm-svn: 365010

1 files changed, 204 insertions, 194 deletions

diff --git a/llvm/test/CodeGen/ARM/sub-of-not.ll b/llvm/test/CodeGen/ARM/sub-of-not.ll
index 853a79aeb95..f9599f17efd 100644
--- a/llvm/test/CodeGen/ARM/sub-of-not.ll
+++ b/llvm/test/CodeGen/ARM/sub-of-not.ll
@@ -14,15 +14,21 @@
 define i8 @scalar_i8(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    mvn r0, r0
-; ARM-NEXT:    sub r0, r1, r0
+; ARM-NEXT:    add r0, r1, r0
+; ARM-NEXT:    add r0, r0, #1
 ; ARM-NEXT:    bx lr
 ;
-; THUMB-LABEL: scalar_i8:
-; THUMB:       @ %bb.0:
-; THUMB-NEXT:    mvns r0, r0
-; THUMB-NEXT:    subs r0, r1, r0
-; THUMB-NEXT:    bx lr
+; THUMB6-LABEL: scalar_i8:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    adds r0, r1, r0
+; THUMB6-NEXT:    adds r0, r0, #1
+; THUMB6-NEXT:    bx lr
+;
+; THUMB78-LABEL: scalar_i8:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    add r0, r1
+; THUMB78-NEXT:    adds r0, #1
+; THUMB78-NEXT:    bx lr
   %t0 = xor i8 %x, -1
   %t1 = sub i8 %y, %t0
   ret i8 %t1
@@ -31,15 +37,21 @@ define i8 @scalar_i8(i8 %x, i8 %y) nounwind {
 define i16 @scalar_i16(i16 %x, i16 %y) nounwind {
 ; ARM-LABEL: scalar_i16:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    mvn r0, r0
-; ARM-NEXT:    sub r0, r1, r0
+; ARM-NEXT:    add r0, r1, r0
+; ARM-NEXT:    add r0, r0, #1
 ; ARM-NEXT:    bx lr
 ;
-; THUMB-LABEL: scalar_i16:
-; THUMB:       @ %bb.0:
-; THUMB-NEXT:    mvns r0, r0
-; THUMB-NEXT:    subs r0, r1, r0
-; THUMB-NEXT:    bx lr
+; THUMB6-LABEL: scalar_i16:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    adds r0, r1, r0
+; THUMB6-NEXT:    adds r0, r0, #1
+; THUMB6-NEXT:    bx lr
+;
+; THUMB78-LABEL: scalar_i16:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    add r0, r1
+; THUMB78-NEXT:    adds r0, #1
+; THUMB78-NEXT:    bx lr
   %t0 = xor i16 %x, -1
   %t1 = sub i16 %y, %t0
   ret i16 %t1
@@ -48,15 +60,21 @@ define i16 @scalar_i16(i16 %x, i16 %y) nounwind {
 define i32 @scalar_i32(i32 %x, i32 %y) nounwind {
 ; ARM-LABEL: scalar_i32:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    mvn r0, r0
-; ARM-NEXT:    sub r0, r1, r0
+; ARM-NEXT:    add r0, r1, r0
+; ARM-NEXT:    add r0, r0, #1
 ; ARM-NEXT:    bx lr
 ;
-; THUMB-LABEL: scalar_i32:
-; THUMB:       @ %bb.0:
-; THUMB-NEXT:    mvns r0, r0
-; THUMB-NEXT:    subs r0, r1, r0
-; THUMB-NEXT:    bx lr
+; THUMB6-LABEL: scalar_i32:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    adds r0, r1, r0
+; THUMB6-NEXT:    adds r0, r0, #1
+; THUMB6-NEXT:    bx lr
+;
+; THUMB78-LABEL: scalar_i32:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    add r0, r1
+; THUMB78-NEXT:    adds r0, #1
+; THUMB78-NEXT:    bx lr
   %t0 = xor i32 %x, -1
   %t1 = sub i32 %y, %t0
   ret i32 %t1
@@ -65,10 +83,10 @@ define i32 @scalar_i32(i32 %x, i32 %y) nounwind {
 define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
 ; ARM-LABEL: scalar_i64:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    mvn r0, r0
-; ARM-NEXT:    mvn r1, r1
-; ARM-NEXT:    subs r0, r2, r0
-; ARM-NEXT:    sbc r1, r3, r1
+; ARM-NEXT:    adds r0, r2, r0
+; ARM-NEXT:    adc r1, r3, r1
+; ARM-NEXT:    adds r0, r0, #1
+; ARM-NEXT:    adc r1, r1, #0
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: scalar_i64:
@@ -80,21 +98,13 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
 ; THUMB6-NEXT:    mov r1, r3
 ; THUMB6-NEXT:    bx lr
 ;
-; THUMB7-LABEL: scalar_i64:
-; THUMB7:       @ %bb.0:
-; THUMB7-NEXT:    mvns r0, r0
-; THUMB7-NEXT:    mvns r1, r1
-; THUMB7-NEXT:    subs r0, r2, r0
-; THUMB7-NEXT:    sbc.w r1, r3, r1
-; THUMB7-NEXT:    bx lr
-;
-; THUMB8-LABEL: scalar_i64:
-; THUMB8:       @ %bb.0:
-; THUMB8-NEXT:    mvns r1, r1
-; THUMB8-NEXT:    mvns r0, r0
-; THUMB8-NEXT:    subs r0, r2, r0
-; THUMB8-NEXT:    sbc.w r1, r3, r1
-; THUMB8-NEXT:    bx lr
+; THUMB78-LABEL: scalar_i64:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    adds r0, r0, r2
+; THUMB78-NEXT:    adcs r1, r3
+; THUMB78-NEXT:    adds r0, #1
+; THUMB78-NEXT:    adc r1, r1, #0
+; THUMB78-NEXT:    bx lr
   %t0 = xor i64 %x, -1
   %t1 = sub i64 %y, %t0
   ret i64 %t1
@@ -103,83 +113,83 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
 define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
 ; ARM6-LABEL: vector_i128_i8:
 ; ARM6:       @ %bb.0:
-; ARM6-NEXT:    ldrb r1, [sp, #52]
-; ARM6-NEXT:    mvn r12, r1
+; ARM6-NEXT:    ldrb r12, [sp, #52]
 ; ARM6-NEXT:    ldrb r1, [sp, #116]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #48]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #15]
-; ARM6-NEXT:    ldrb r1, [sp, #48]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #112]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #44]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #14]
-; ARM6-NEXT:    ldrb r1, [sp, #44]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #108]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #40]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #13]
-; ARM6-NEXT:    ldrb r1, [sp, #40]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #104]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #36]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #12]
-; ARM6-NEXT:    ldrb r1, [sp, #36]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #100]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #32]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #11]
-; ARM6-NEXT:    ldrb r1, [sp, #32]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #96]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #28]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #10]
-; ARM6-NEXT:    ldrb r1, [sp, #28]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #92]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #24]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #9]
-; ARM6-NEXT:    ldrb r1, [sp, #24]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #88]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #20]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #8]
-; ARM6-NEXT:    ldrb r1, [sp, #20]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #84]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #16]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #7]
-; ARM6-NEXT:    ldrb r1, [sp, #16]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #80]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #12]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #6]
-; ARM6-NEXT:    ldrb r1, [sp, #12]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #76]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #8]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #5]
-; ARM6-NEXT:    ldrb r1, [sp, #8]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #72]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp, #4]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #4]
-; ARM6-NEXT:    ldrb r1, [sp, #4]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #68]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrb r12, [sp]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #3]
-; ARM6-NEXT:    ldrb r1, [sp]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrb r1, [sp, #64]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #2]
-; ARM6-NEXT:    mvn r1, r3
-; ARM6-NEXT:    ldrb r3, [sp, #60]
-; ARM6-NEXT:    sub r1, r3, r1
+; ARM6-NEXT:    ldrb r1, [sp, #60]
+; ARM6-NEXT:    add r1, r1, r3
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0, #1]
-; ARM6-NEXT:    mvn r1, r2
-; ARM6-NEXT:    ldrb r2, [sp, #56]
-; ARM6-NEXT:    sub r1, r2, r1
+; ARM6-NEXT:    ldrb r1, [sp, #56]
+; ARM6-NEXT:    add r1, r1, r2
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strb r1, [r0]
 ; ARM6-NEXT:    bx lr
 ;
@@ -199,82 +209,82 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    push {r4, lr}
 ; THUMB6-NEXT:    ldr r1, [sp, #60]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #124]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #15]
 ; THUMB6-NEXT:    ldr r1, [sp, #56]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #120]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #14]
 ; THUMB6-NEXT:    ldr r1, [sp, #52]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #116]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #13]
 ; THUMB6-NEXT:    ldr r1, [sp, #48]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #112]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #12]
 ; THUMB6-NEXT:    ldr r1, [sp, #44]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #108]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #11]
 ; THUMB6-NEXT:    ldr r1, [sp, #40]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #104]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #10]
 ; THUMB6-NEXT:    ldr r1, [sp, #36]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #100]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #9]
 ; THUMB6-NEXT:    ldr r1, [sp, #32]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #96]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #8]
 ; THUMB6-NEXT:    ldr r1, [sp, #28]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #92]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #7]
 ; THUMB6-NEXT:    ldr r1, [sp, #24]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #88]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #6]
 ; THUMB6-NEXT:    ldr r1, [sp, #20]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #84]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #5]
 ; THUMB6-NEXT:    ldr r1, [sp, #16]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #80]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #4]
 ; THUMB6-NEXT:    ldr r1, [sp, #12]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #76]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #3]
 ; THUMB6-NEXT:    ldr r1, [sp, #8]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #72]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #2]
-; THUMB6-NEXT:    mvns r1, r3
-; THUMB6-NEXT:    ldr r3, [sp, #68]
-; THUMB6-NEXT:    subs r1, r3, r1
+; THUMB6-NEXT:    ldr r1, [sp, #68]
+; THUMB6-NEXT:    adds r1, r1, r3
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0, #1]
-; THUMB6-NEXT:    mvns r1, r2
-; THUMB6-NEXT:    ldr r2, [sp, #64]
-; THUMB6-NEXT:    subs r1, r2, r1
+; THUMB6-NEXT:    ldr r1, [sp, #64]
+; THUMB6-NEXT:    adds r1, r1, r2
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strb r1, [r0]
 ; THUMB6-NEXT:    pop {r4, pc}
 ;
@@ -297,43 +307,43 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
 define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; ARM6-LABEL: vector_i128_i16:
 ; ARM6:       @ %bb.0:
-; ARM6-NEXT:    ldrh r1, [sp, #20]
-; ARM6-NEXT:    mvn r12, r1
+; ARM6-NEXT:    ldrh r12, [sp, #20]
 ; ARM6-NEXT:    ldrh r1, [sp, #52]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrh r12, [sp, #16]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #14]
-; ARM6-NEXT:    ldrh r1, [sp, #16]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrh r1, [sp, #48]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrh r12, [sp, #12]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #12]
-; ARM6-NEXT:    ldrh r1, [sp, #12]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrh r1, [sp, #44]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrh r12, [sp, #8]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #10]
-; ARM6-NEXT:    ldrh r1, [sp, #8]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrh r1, [sp, #40]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrh r12, [sp, #4]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #8]
-; ARM6-NEXT:    ldrh r1, [sp, #4]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrh r1, [sp, #36]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    ldrh r12, [sp]
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #6]
-; ARM6-NEXT:    ldrh r1, [sp]
-; ARM6-NEXT:    mvn r12, r1
 ; ARM6-NEXT:    ldrh r1, [sp, #32]
-; ARM6-NEXT:    sub r1, r1, r12
+; ARM6-NEXT:    add r1, r1, r12
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #4]
-; ARM6-NEXT:    mvn r1, r3
-; ARM6-NEXT:    ldrh r3, [sp, #28]
-; ARM6-NEXT:    sub r1, r3, r1
+; ARM6-NEXT:    ldrh r1, [sp, #28]
+; ARM6-NEXT:    add r1, r1, r3
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0, #2]
-; ARM6-NEXT:    mvn r1, r2
-; ARM6-NEXT:    ldrh r2, [sp, #24]
-; ARM6-NEXT:    sub r1, r2, r1
+; ARM6-NEXT:    ldrh r1, [sp, #24]
+; ARM6-NEXT:    add r1, r1, r2
+; ARM6-NEXT:    add r1, r1, #1
 ; ARM6-NEXT:    strh r1, [r0]
 ; ARM6-NEXT:    bx lr
 ;
@@ -353,42 +363,42 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    push {r4, lr}
 ; THUMB6-NEXT:    ldr r1, [sp, #28]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #60]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #14]
 ; THUMB6-NEXT:    ldr r1, [sp, #24]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #56]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #12]
 ; THUMB6-NEXT:    ldr r1, [sp, #20]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #52]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #10]
 ; THUMB6-NEXT:    ldr r1, [sp, #16]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #48]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #8]
 ; THUMB6-NEXT:    ldr r1, [sp, #12]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #44]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #6]
 ; THUMB6-NEXT:    ldr r1, [sp, #8]
-; THUMB6-NEXT:    mvns r1, r1
 ; THUMB6-NEXT:    ldr r4, [sp, #40]
-; THUMB6-NEXT:    subs r1, r4, r1
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #4]
-; THUMB6-NEXT:    mvns r1, r3
-; THUMB6-NEXT:    ldr r3, [sp, #36]
-; THUMB6-NEXT:    subs r1, r3, r1
+; THUMB6-NEXT:    ldr r1, [sp, #36]
+; THUMB6-NEXT:    adds r1, r1, r3
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0, #2]
-; THUMB6-NEXT:    mvns r1, r2
-; THUMB6-NEXT:    ldr r2, [sp, #32]
-; THUMB6-NEXT:    subs r1, r2, r1
+; THUMB6-NEXT:    ldr r1, [sp, #32]
+; THUMB6-NEXT:    adds r1, r1, r2
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    strh r1, [r0]
 ; THUMB6-NEXT:    pop {r4, pc}
 ;
@@ -411,18 +421,18 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; ARM6-LABEL: vector_i128_i32:
 ; ARM6:       @ %bb.0:
-; ARM6-NEXT:    mvn r12, r0
-; ARM6-NEXT:    ldr r0, [sp]
-; ARM6-NEXT:    sub r0, r0, r12
-; ARM6-NEXT:    mvn r12, r1
-; ARM6-NEXT:    ldr r1, [sp, #4]
-; ARM6-NEXT:    sub r1, r1, r12
-; ARM6-NEXT:    mvn r12, r2
-; ARM6-NEXT:    ldr r2, [sp, #8]
-; ARM6-NEXT:    sub r2, r2, r12
-; ARM6-NEXT:    mvn r12, r3
-; ARM6-NEXT:    ldr r3, [sp, #12]
-; ARM6-NEXT:    sub r3, r3, r12
+; ARM6-NEXT:    ldr r12, [sp]
+; ARM6-NEXT:    add r0, r12, r0
+; ARM6-NEXT:    ldr r12, [sp, #4]
+; ARM6-NEXT:    add r0, r0, #1
+; ARM6-NEXT:    add r1, r12, r1
+; ARM6-NEXT:    ldr r12, [sp, #8]
+; ARM6-NEXT:    add r1, r1, #1
+; ARM6-NEXT:    add r2, r12, r2
+; ARM6-NEXT:    ldr r12, [sp, #12]
+; ARM6-NEXT:    add r2, r2, #1
+; ARM6-NEXT:    add r3, r12, r3
+; ARM6-NEXT:    add r3, r3, #1
 ; ARM6-NEXT:    bx lr
 ;
 ; ARM78-LABEL: vector_i128_i32:
@@ -440,18 +450,18 @@ define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; THUMB6-LABEL: vector_i128_i32:
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    push {r4, lr}
-; THUMB6-NEXT:    mvns r0, r0
 ; THUMB6-NEXT:    ldr r4, [sp, #8]
-; THUMB6-NEXT:    subs r0, r4, r0
-; THUMB6-NEXT:    mvns r1, r1
+; THUMB6-NEXT:    adds r0, r4, r0
+; THUMB6-NEXT:    adds r0, r0, #1
 ; THUMB6-NEXT:    ldr r4, [sp, #12]
-; THUMB6-NEXT:    subs r1, r4, r1
-; THUMB6-NEXT:    mvns r2, r2
+; THUMB6-NEXT:    adds r1, r4, r1
+; THUMB6-NEXT:    adds r1, r1, #1
 ; THUMB6-NEXT:    ldr r4, [sp, #16]
-; THUMB6-NEXT:    subs r2, r4, r2
-; THUMB6-NEXT:    mvns r3, r3
+; THUMB6-NEXT:    adds r2, r4, r2
+; THUMB6-NEXT:    adds r2, r2, #1
 ; THUMB6-NEXT:    ldr r4, [sp, #20]
-; THUMB6-NEXT:    subs r3, r4, r3
+; THUMB6-NEXT:    adds r3, r4, r3
+; THUMB6-NEXT:    adds r3, r3, #1
 ; THUMB6-NEXT:    pop {r4, pc}
 ;
 ; THUMB78-LABEL: vector_i128_i32:
@@ -474,18 +484,18 @@ define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; ARM6-LABEL: vector_i128_i64:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    push {r11, lr}
-; ARM6-NEXT:    mvn lr, r1
-; ARM6-NEXT:    ldr r1, [sp, #8]
-; ARM6-NEXT:    mvn r0, r0
+; ARM6-NEXT:    ldr lr, [sp, #8]
 ; ARM6-NEXT:    ldr r12, [sp, #12]
-; ARM6-NEXT:    subs r0, r1, r0
-; ARM6-NEXT:    mvn r2, r2
-; ARM6-NEXT:    sbc r1, r12, lr
-; ARM6-NEXT:    mvn lr, r3
-; ARM6-NEXT:    ldr r3, [sp, #16]
+; ARM6-NEXT:    adds r0, lr, r0
+; ARM6-NEXT:    ldr lr, [sp, #16]
+; ARM6-NEXT:    adc r1, r12, r1
+; ARM6-NEXT:    adds r0, r0, #1
 ; ARM6-NEXT:    ldr r12, [sp, #20]
-; ARM6-NEXT:    subs r2, r3, r2
-; ARM6-NEXT:    sbc r3, r12, lr
+; ARM6-NEXT:    adc r1, r1, #0
+; ARM6-NEXT:    adds r2, lr, r2
+; ARM6-NEXT:    adc r3, r12, r3
+; ARM6-NEXT:    adds r2, r2, #1
+; ARM6-NEXT:    adc r3, r3, #0
 ; ARM6-NEXT:    pop {r11, pc}
 ;
 ; ARM78-LABEL: vector_i128_i64: