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| author | Jim Grosbach <grosbach@apple.com> | 2010-12-09 18:31:13 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-12-09 18:31:13 +0000 |
| commit | 5fccad84a31602007d5d65606e7470bff9501bdf (patch) | |
| tree | 9753838b83b160eb598dfd8ab97f6d0d2d418054 /llvm/test/CodeGen/ARM/str_pre-2.ll | |
| parent | 38c3ca78e63deca89d16d2d2317570e55c5fb2a1 (diff) | |
| download | bcm5719-llvm-5fccad84a31602007d5d65606e7470bff9501bdf.tar.gz bcm5719-llvm-5fccad84a31602007d5d65606e7470bff9501bdf.zip | |
ARM stm/ldm instructions require more than one register in the register list.
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
llvm-svn: 121391
Diffstat (limited to 'llvm/test/CodeGen/ARM/str_pre-2.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/str_pre-2.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM/str_pre-2.ll b/llvm/test/CodeGen/ARM/str_pre-2.ll index a79cf9bf7f8..4f9ba4db4c2 100644 --- a/llvm/test/CodeGen/ARM/str_pre-2.ll +++ b/llvm/test/CodeGen/ARM/str_pre-2.ll @@ -4,8 +4,8 @@ define i64 @t(i64 %a) nounwind readonly { entry: -; CHECK: push {lr} -; CHECK: ldmia sp!, {pc} +; CHECK: str lr, [sp, #-4]! +; CHECK: ldr lr, [sp], #4 %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 %2 = mul i64 %1, %a |
