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author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
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committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/ARM/shifter_operand.ll | |
parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/ARM/shifter_operand.ll')
-rw-r--r-- | llvm/test/CodeGen/ARM/shifter_operand.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index fd09d822d65..3999168de6b 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -43,8 +43,8 @@ entry: %tmp3 = inttoptr i32 %tmp2 to i32* %tmp4 = add i32 %base2, %tmp1 %tmp5 = inttoptr i32 %tmp4 to i32* - %tmp6 = load i32* %tmp3 - %tmp7 = load i32* %tmp5 + %tmp6 = load i32, i32* %tmp3 + %tmp7 = load i32, i32* %tmp5 %tmp8 = add i32 %tmp7, %tmp6 ret i32 %tmp8 } @@ -68,7 +68,7 @@ entry: %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 %3 = getelementptr inbounds i32, i32* %1, i32 %2 - %4 = load i32* %3, align 4 + %4 = load i32, i32* %3, align 4 %5 = add nsw i32 %4, 1 store i32 %5, i32* %3, align 4 ret void |