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| author | Cameron Zwarich <zwarich@apple.com> | 2011-10-05 23:38:50 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-10-05 23:38:50 +0000 |
| commit | 87aa18378e6aa5d7be4679cdfb17fdfdb29e29b9 (patch) | |
| tree | f4f71acfcbfe964175ff7809ae5a18204d8d0245 /llvm/test/CodeGen/ARM/shifter_operand.ll | |
| parent | 77f8661d18af100fe95fd618ecc01862ed8505f4 (diff) | |
| download | bcm5719-llvm-87aa18378e6aa5d7be4679cdfb17fdfdb29e29b9.tar.gz bcm5719-llvm-87aa18378e6aa5d7be4679cdfb17fdfdb29e29b9.zip | |
Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
Diffstat (limited to 'llvm/test/CodeGen/ARM/shifter_operand.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/shifter_operand.ll | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index f0e2d102610..964cef084f1 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -54,13 +54,12 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr r2, [r0, r1, lsl #2] -; A8: str r2, [r0, r1, lsl #2] +; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A8: str [[REG]], [r0, r1, lsl #2] ; A9: test4: -; A9: add r0, r0, r{{[0-9]+}}, lsl #2 -; A9: ldr r1, [r0] -; A9: str r1, [r0] +; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A9: str [[REG]], [r0, r1, lsl #2] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 |
