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| author | Sanjay Patel <spatel@rotateright.com> | 2017-04-05 14:09:39 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-04-05 14:09:39 +0000 |
| commit | b2f1621bb1edf6f054fdc0b5e2771dfdd79ca87a (patch) | |
| tree | e7ff57963aaa2ddc9bed96766e8e9293983c34e5 /llvm/test/CodeGen/ARM/setcc-logic.ll | |
| parent | 6615f2b3d673e422789287bb7ae097df00ca32a1 (diff) | |
| download | bcm5719-llvm-b2f1621bb1edf6f054fdc0b5e2771dfdd79ca87a.tar.gz bcm5719-llvm-b2f1621bb1edf6f054fdc0b5e2771dfdd79ca87a.zip | |
[DAGCombiner] add and use TLI hook to convert and-of-seteq / or-of-setne to bitwise logic+setcc (PR32401)
This is a generic combine enabled via target hook to reduce icmp logic as discussed in:
https://bugs.llvm.org/show_bug.cgi?id=32401
It's likely that other targets will want to enable this hook for scalar transforms,
and there are probably other patterns that can use bitwise logic to reduce comparisons.
Note that we are missing an IR canonicalization for these patterns, and we will probably
prefer the pair-of-compares form in IR (shorter, more likely to fold).
Differential Revision: https://reviews.llvm.org/D31483
llvm-svn: 299542
Diffstat (limited to 'llvm/test/CodeGen/ARM/setcc-logic.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/setcc-logic.ll | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/ARM/setcc-logic.ll b/llvm/test/CodeGen/ARM/setcc-logic.ll index bfd188fb10d..79bae1facb3 100644 --- a/llvm/test/CodeGen/ARM/setcc-logic.ll +++ b/llvm/test/CodeGen/ARM/setcc-logic.ll @@ -20,13 +20,11 @@ define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind { define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: and_eq: ; CHECK: @ BB#0: -; CHECK-NEXT: cmp r2, r3 -; CHECK-NEXT: mov r2, #0 -; CHECK-NEXT: movweq r2, #1 -; CHECK-NEXT: mov r12, #0 -; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: movweq r12, #1 -; CHECK-NEXT: and r0, r12, r2 +; CHECK-NEXT: eor r2, r2, r3 +; CHECK-NEXT: eor r0, r0, r1 +; CHECK-NEXT: orrs r0, r0, r2 +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: movweq r0, #1 ; CHECK-NEXT: bx lr %cmp1 = icmp eq i32 %a, %b %cmp2 = icmp eq i32 %c, %d @@ -37,13 +35,10 @@ define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: or_ne: ; CHECK: @ BB#0: -; CHECK-NEXT: cmp r2, r3 -; CHECK-NEXT: mov r2, #0 -; CHECK-NEXT: movwne r2, #1 -; CHECK-NEXT: mov r12, #0 -; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: movwne r12, #1 -; CHECK-NEXT: orr r0, r12, r2 +; CHECK-NEXT: eor r2, r2, r3 +; CHECK-NEXT: eor r0, r0, r1 +; CHECK-NEXT: orrs r0, r0, r2 +; CHECK-NEXT: movwne r0, #1 ; CHECK-NEXT: bx lr %cmp1 = icmp ne i32 %a, %b %cmp2 = icmp ne i32 %c, %d |
