[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).

The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide range of cores.

As is to be expected, quite a few small adaptations are needed to the
regressions tests, as the difference in scheduling results in:
- Quite a few small instruction schedule differences.
- A few changes in register allocation decisions caused by different
 instruction schedules.
- A few changes in IfConversion decisions, due to a difference in
 instruction schedule and/or the estimated cost of a branch mispredict.

llvm-svn: 306514

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/test/CodeGen/ARM/select_const.ll b/llvm/test/CodeGen/ARM/select_const.ll
index 48fe572bf8a..23de9c35a5b 100644
--- a/llvm/test/CodeGen/ARM/select_const.ll
+++ b/llvm/test/CodeGen/ARM/select_const.ll
@@ -281,16 +281,16 @@ define i64 @opaque_constant1(i1 %cond, i64 %x) {
 ; CHECK:       @ BB#0:
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
-; CHECK-NEXT:    ands r12, r0, #1
 ; CHECK-NEXT:    mov lr, #1
+; CHECK-NEXT:    ands r12, r0, #1
 ; CHECK-NEXT:    mov r0, #23
-; CHECK-NEXT:    eor r3, r3, #1
 ; CHECK-NEXT:    orr lr, lr, #65536
 ; CHECK-NEXT:    mvnne r0, #3
-; CHECK-NEXT:    movne r12, #1
 ; CHECK-NEXT:    and r4, r0, lr
-; CHECK-NEXT:    eor r2, r2, lr
+; CHECK-NEXT:    movne r12, #1
 ; CHECK-NEXT:    subs r0, r4, #1
+; CHECK-NEXT:    eor r2, r2, lr
+; CHECK-NEXT:    eor r3, r3, #1
 ; CHECK-NEXT:    sbc r1, r12, #0
 ; CHECK-NEXT:    orrs r2, r2, r3
 ; CHECK-NEXT:    movne r0, r4