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| author | Sanjay Patel <spatel@rotateright.com> | 2017-02-27 21:30:54 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-02-27 21:30:54 +0000 |
| commit | ae7873fe551b4bd0cfc24f86f9d82fb688e96297 (patch) | |
| tree | 2e2b44bc002d1c0ee7053e6784b4b2a0eefc88c7 /llvm/test/CodeGen/ARM/select_const.ll | |
| parent | b7acfc0139bba6f5fdc3f4c409411f03dce543ab (diff) | |
| download | bcm5719-llvm-ae7873fe551b4bd0cfc24f86f9d82fb688e96297.tar.gz bcm5719-llvm-ae7873fe551b4bd0cfc24f86f9d82fb688e96297.zip | |
[ARM] don't transform an add(ext Cond), C to select unless there's a setcc of the condition
The transform in question claims to be doing:
// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
...starting in PerformADDCombineWithOperands(), but it wasn't actually checking for a setcc node
for the sext/zext patterns.
This is exactly the opposite of a transform I'd like to add to DAGCombiner's foldSelectOfConstants(),
so I was seeing infinite loops with my draft of a patch applied.
The changes in select_const.ll look positive (less instructions). The change in arm-and-tst-peephole.ll
is unrelated. We're changing the input IR in that test to preserve the intent of the test, but that's
not affected by this code change.
Differential Revision:
https://reviews.llvm.org/D30355
llvm-svn: 296389
Diffstat (limited to 'llvm/test/CodeGen/ARM/select_const.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/select_const.ll | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/ARM/select_const.ll b/llvm/test/CodeGen/ARM/select_const.ll index 50c36310b2c..52d9af0399c 100644 --- a/llvm/test/CodeGen/ARM/select_const.ll +++ b/llvm/test/CodeGen/ARM/select_const.ll @@ -98,9 +98,8 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { define i32 @select_0_or_neg1_alt(i1 %cond) { ; CHECK-LABEL: select_0_or_neg1_alt: ; CHECK: @ BB#0: -; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: bic r0, r1, r0 -; CHECK-NEXT: rsb r0, r0, #0 +; CHECK-NEXT: and r0, r0, #1 +; CHECK-NEXT: sub r0, r0, #1 ; CHECK-NEXT: mov pc, lr %z = zext i1 %cond to i32 %add = add i32 %z, -1 @@ -110,8 +109,7 @@ define i32 @select_0_or_neg1_alt(i1 %cond) { define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_0_or_neg1_alt_zeroext: ; CHECK: @ BB#0: -; CHECK-NEXT: eor r0, r0, #1 -; CHECK-NEXT: rsb r0, r0, #0 +; CHECK-NEXT: sub r0, r0, #1 ; CHECK-NEXT: mov pc, lr %z = zext i1 %cond to i32 %add = add i32 %z, -1 |
