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authorAndrew Zhogin <andrew.zhogin@gmail.com>2017-07-05 17:55:42 +0000
committerAndrew Zhogin <andrew.zhogin@gmail.com>2017-07-05 17:55:42 +0000
commit45d192823ec0bc5ea40cd6af8e1ac00393cc0e21 (patch)
tree50aa33e12fc8f8621ad6bdcd0e661b1aad30bb53 /llvm/test/CodeGen/ARM/ror.ll
parentd7faa9165f5edbe31ec72c7d79b4c368c1e9e1e2 (diff)
downloadbcm5719-llvm-45d192823ec0bc5ea40cd6af8e1ac00393cc0e21.tar.gz
bcm5719-llvm-45d192823ec0bc5ea40cd6af8e1ac00393cc0e21.zip
[DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions into one with combined shift operand.
For two ROTR operations with shifts C1, C2; combined shift operand will be (C1 + C2) % bitsize. Differential revision: https://reviews.llvm.org/D12833 llvm-svn: 307179
Diffstat (limited to 'llvm/test/CodeGen/ARM/ror.ll')
-rw-r--r--llvm/test/CodeGen/ARM/ror.ll9
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/ARM/ror.ll b/llvm/test/CodeGen/ARM/ror.ll
index a6cc415e830..0f699a8dd29 100644
--- a/llvm/test/CodeGen/ARM/ror.ll
+++ b/llvm/test/CodeGen/ARM/ror.ll
@@ -3,8 +3,7 @@
; rotr (rotr x, 4), 6 -> rotr x, 10 -> ror r0, r0, #10
define i32 @test1(i32 %x) nounwind readnone {
; CHECK-LABEL: test1:
-; CHECK: ror r0, r0, #4
-; CHECK: ror r0, r0, #6
+; CHECK: ror r0, r0, #10
; CHECK: bx lr
entry:
%high_part.i = shl i32 %x, 28
@@ -19,10 +18,8 @@ entry:
; the same vector test
define <2 x i32> @test2(<2 x i32> %x) nounwind readnone {
; CHECK-LABEL: test2:
-; CHECK: ror r0, r0, #4
-; CHECK: ror r1, r1, #4
-; CHECK: ror r0, r0, #6
-; CHECK: ror r1, r1, #6
+; CHECK: ror r0, r0, #10
+; CHECK: ror r1, r1, #10
; CHECK: bx lr
entry:
%high_part.i = shl <2 x i32> %x, <i32 28, i32 28>
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