(Re)generate various tests. NFC

llvm-svn: 374074

1 files changed, 38 insertions, 19 deletions

diff --git a/llvm/test/CodeGen/ARM/rev.ll b/llvm/test/CodeGen/ARM/rev.ll
index a36526ff1fb..b97dbc844e0 100644
--- a/llvm/test/CodeGen/ARM/rev.ll
+++ b/llvm/test/CodeGen/ARM/rev.ll
@@ -1,8 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
 
 define i32 @test1(i32 %X) nounwind {
-; CHECK-LABEL: test1
-; CHECK: rev16 r0, r0
+; CHECK-LABEL: test1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    rev16 r0, r0
+; CHECK-NEXT:    bx lr
         %tmp1 = lshr i32 %X, 8
         %X15 = bitcast i32 %X to i32
         %tmp4 = shl i32 %X15, 8
@@ -17,8 +20,10 @@ define i32 @test1(i32 %X) nounwind {
 }
 
 define i32 @test2(i32 %X) nounwind {
-; CHECK-LABEL: test2
-; CHECK: revsh r0, r0
+; CHECK-LABEL: test2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
         %tmp1 = lshr i32 %X, 8
         %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
         %tmp3 = trunc i32 %X to i16
@@ -31,9 +36,11 @@ define i32 @test2(i32 %X) nounwind {
 
 ; rdar://9147637
 define i32 @test3(i16 zeroext %a) nounwind {
-entry:
 ; CHECK-LABEL: test3:
-; CHECK: revsh r0, r0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
+entry:
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   %1 = sext i16 %0 to i32
   ret i32 %1
@@ -42,9 +49,11 @@ entry:
 declare i16 @llvm.bswap.i16(i16) nounwind readnone
 
 define i32 @test4(i16 zeroext %a) nounwind {
-entry:
 ; CHECK-LABEL: test4:
-; CHECK: revsh r0, r0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
+entry:
   %conv = zext i16 %a to i32
   %shr9 = lshr i16 %a, 8
   %conv2 = zext i16 %shr9 to i32
@@ -57,9 +66,11 @@ entry:
 
 ; rdar://9609059
 define i32 @test5(i32 %i) nounwind readnone {
+; CHECK-LABEL: test5:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK-LABEL: test5
-; CHECK: revsh r0, r0
   %shl = shl i32 %i, 24
   %shr = ashr exact i32 %shl, 16
   %shr23 = lshr i32 %i, 8
@@ -70,9 +81,11 @@ entry:
 
 ; rdar://9609108
 define i32 @test6(i32 %x) nounwind readnone {
+; CHECK-LABEL: test6:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    rev16 r0, r0
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK-LABEL: test6
-; CHECK: rev16 r0, r0
   %and = shl i32 %x, 8
   %shl = and i32 %and, 65280
   %and2 = lshr i32 %x, 8
@@ -87,10 +100,12 @@ entry:
 
 ; rdar://9164521
 define i32 @test7(i32 %a) nounwind readnone {
+; CHECK-LABEL: test7:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    rev r0, r0
+; CHECK-NEXT:    lsr r0, r0, #16
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK-LABEL: test7
-; CHECK: rev r0, r0
-; CHECK: lsr r0, r0, #16
   %and = lshr i32 %a, 8
   %shr3 = and i32 %and, 255
   %and2 = shl i32 %a, 8
@@ -100,9 +115,11 @@ entry:
 }
 
 define i32 @test8(i32 %a) nounwind readnone {
+; CHECK-LABEL: test8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK-LABEL: test8
-; CHECK: revsh r0, r0
   %and = lshr i32 %a, 8
   %shr4 = and i32 %and, 255
   %and2 = shl i32 %a, 8
@@ -114,9 +131,11 @@ entry:
 
 ; rdar://10750814
 define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {
+; CHECK-LABEL: test9:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    rev16 r0, r0
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK-LABEL: test9
-; CHECK: rev16 r0, r0
   %conv = zext i16 %v to i32
   %shr4 = lshr i32 %conv, 8
   %shl = shl nuw nsw i32 %conv, 8