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| author | Tim Northover <tnorthover@apple.com> | 2013-08-20 08:57:11 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-08-20 08:57:11 +0000 |
| commit | f79c3a5aefefaf7de1b4c5787871f09d947d85f1 (patch) | |
| tree | 37332ee67624c468b2c2379b3218dec63b8fd78e /llvm/test/CodeGen/ARM/reg_sequence.ll | |
| parent | dc985ef0af6fe5d73bfc5bd5b470b6edddd4ac77 (diff) | |
| download | bcm5719-llvm-f79c3a5aefefaf7de1b4c5787871f09d947d85f1.tar.gz bcm5719-llvm-f79c3a5aefefaf7de1b4c5787871f09d947d85f1.zip | |
ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.
llvm-svn: 188773
Diffstat (limited to 'llvm/test/CodeGen/ARM/reg_sequence.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/reg_sequence.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index 3fe2bb8e382..25484f48485 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -239,10 +239,9 @@ bb14: ; preds = %bb6 ; PR7157 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK-LABEL: t9: -; CHECK: vldr -; CHECK-NOT: vmov d{{.*}}, d16 -; CHECK: vmov.i32 d17 +; CHECK: vmov.i32 d16, #0x0 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] +; CHECK-NEXT: vorr d17, d16, d16 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] |
