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| author | Evan Cheng <evan.cheng@apple.com> | 2012-09-18 01:42:45 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-09-18 01:42:45 +0000 |
| commit | 90ae8f84421e24be66a1dd90a79ccdf54ee44d1d (patch) | |
| tree | 91bba67310d2791a9675467bec44e7876507a9d9 /llvm/test/CodeGen/ARM/reg_sequence.ll | |
| parent | 9150610db7928b4dfe22a8f3e83cef15a6cf6986 (diff) | |
| download | bcm5719-llvm-90ae8f84421e24be66a1dd90a79ccdf54ee44d1d.tar.gz bcm5719-llvm-90ae8f84421e24be66a1dd90a79ccdf54ee44d1d.zip | |
Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte
aligned address. Based on patch by David Peixotto.
Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782
llvm-svn: 164089
Diffstat (limited to 'llvm/test/CodeGen/ARM/reg_sequence.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/reg_sequence.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index 05794e4ebdd..92c0f0a18ce 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -137,7 +137,7 @@ return2: define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK: t5: -; CHECK: vldmia +; CHECK: vld1.32 ; How can FileCheck match Q and D registers? We need a lisp interpreter. ; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov @@ -243,8 +243,8 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: vldr ; CHECK-NOT: vmov d{{.*}}, d16 ; CHECK: vmov.i32 d17 -; CHECK-NEXT: vstmia r0, {d16, d17} -; CHECK-NEXT: vstmia r0, {d16, d17} +; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128] +; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128] %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] store <4 x float> %4, <4 x float>* undef, align 16 |
