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| author | Sanjay Patel <spatel@rotateright.com> | 2019-04-03 13:42:06 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-04-03 13:42:06 +0000 |
| commit | 00dae6b22d2a573d83b77ca7d805e5c334ac3c30 (patch) | |
| tree | e461f63343b50e74535eaf9d7f27be91012169e1 /llvm/test/CodeGen/ARM/reg_sequence.ll | |
| parent | f36b2534b23cc762d3e703802e143d04c4a8cd84 (diff) | |
| download | bcm5719-llvm-00dae6b22d2a573d83b77ca7d805e5c334ac3c30.tar.gz bcm5719-llvm-00dae6b22d2a573d83b77ca7d805e5c334ac3c30.zip | |
[DAGCombiner] loosen restrictions for moving shuffles after vector binop
There are 3 changes to make this correspond to the same transform in instcombine:
1. Remove the legality check - we can't create anything less legal than we started with.
2. Ease the use restriction, so we only bail out if both operands have >1 use.
3. Ease the use restriction for binops with a repeated operand (eg, mul x, x).
As discussed in D60150, there's a scalarization opportunity that will be made
easier by allowing this transform more generally.
llvm-svn: 357580
Diffstat (limited to 'llvm/test/CodeGen/ARM/reg_sequence.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/reg_sequence.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index 97bd654af0d..a54dd0fe79f 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -273,7 +273,7 @@ define arm_aapcs_vfpcc i32 @t10(float %x) nounwind { entry: ; CHECK-LABEL: t10: ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 -; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]] +; CHECK: vmul.f32 q8, q9, d1[0] ; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float %x, i32 1 ; <<4 x float>> [#uses=1] |
