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| author | Vadzim Dambrouski <pftbest@gmail.com> | 2018-07-02 21:05:26 +0000 |
|---|---|---|
| committer | Vadzim Dambrouski <pftbest@gmail.com> | 2018-07-02 21:05:26 +0000 |
| commit | fd10286e047d1264d531fb829915b60359436c86 (patch) | |
| tree | 7212287a7ea0bb47cd419fe1f20bb1b8f4d6fc64 /llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll | |
| parent | b2144058a64b4287b76c2cd3d403ad5b5513d64d (diff) | |
| download | bcm5719-llvm-fd10286e047d1264d531fb829915b60359436c86.tar.gz bcm5719-llvm-fd10286e047d1264d531fb829915b60359436c86.zip | |
[ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.
Reviewers: efriedma, rogfer01, javed.absar
Reviewed By: efriedma, rogfer01
Subscribers: kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D48846
llvm-svn: 336144
Diffstat (limited to 'llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll b/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll index cff5b8998e4..048a1205feb 100644 --- a/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll +++ b/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK-V6M-THUMB define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: sadd: @@ -81,6 +82,8 @@ define i32 @smul(i32 %a, i32 %b) local_unnamed_addr #0 { ; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} ; CHECK-NEXT: cmp r[[RHI]], r0, asr #31 ; CHECK-NEXT: moveq pc, lr +; CHECK-V6M-THUMB-LABEL: smul: +; CHECK-V6M-THUMB: bl __aeabi_lmul entry: %0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b) %1 = extractvalue { i32, i1 } %0, 1 @@ -100,6 +103,8 @@ define i32 @umul(i32 %a, i32 %b) local_unnamed_addr #0 { ; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} ; CHECK-NEXT: cmp r[[RHI]], #0 ; CHECK-NEXT: moveq pc, lr +; CHECK-V6M-THUMB-LABEL: umul: +; CHECK-V6M-THUMB: bl __aeabi_lmul entry: %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) %1 = extractvalue { i32, i1 } %0, 1 |
