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| author | Jeroen Ketema <j.ketema@imperial.ac.uk> | 2015-09-30 10:56:37 +0000 |
|---|---|---|
| committer | Jeroen Ketema <j.ketema@imperial.ac.uk> | 2015-09-30 10:56:37 +0000 |
| commit | ab99b59e8ca28f5366fb95b497e64ae44d67a9ca (patch) | |
| tree | a9b8c1d1af1f1c409aa1e51dcfd9ea96fdf314f1 /llvm/test/CodeGen/ARM/out-of-registers.ll | |
| parent | 42e651fa43747743a6161b1c53e59c743d52a71c (diff) | |
| download | bcm5719-llvm-ab99b59e8ca28f5366fb95b497e64ae44d67a9ca.tar.gz bcm5719-llvm-ab99b59e8ca28f5366fb95b497e64ae44d67a9ca.zip | |
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions
This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234],
vst[234]lane ARM neon intrinsics and associates an address space with the
pointer that these intrinsics take. This changes, e.g.,
<2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32)
to
<2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32)
This change ensures that address spaces are fully taken into account in the ARM
target during lowering of interleaved loads and stores.
Differential Revision: http://reviews.llvm.org/D12985
llvm-svn: 248887
Diffstat (limited to 'llvm/test/CodeGen/ARM/out-of-registers.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/out-of-registers.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/out-of-registers.ll b/llvm/test/CodeGen/ARM/out-of-registers.ll index a83923db0b3..891319881f4 100644 --- a/llvm/test/CodeGen/ARM/out-of-registers.ll +++ b/llvm/test/CodeGen/ARM/out-of-registers.ll @@ -8,7 +8,7 @@ target triple = "thumbv7-none-linux-gnueabi" define void @foo(float* nocapture %A) #0 { %1= bitcast float* %A to i8* - %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8* %1, i32 4) + %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0i8(i8* %1, i32 4) %3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0 %divp_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %3 %4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 1 @@ -17,7 +17,7 @@ define void @foo(float* nocapture %A) #0 { %div8p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %5 %6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 3 %div13p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %6 - tail call void @llvm.arm.neon.vst4.v4f32(i8* %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4) + tail call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4) ret void } @@ -27,8 +27,8 @@ declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1 ; Function Attrs: nounwind readonly ; Function Attrs: nounwind -declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1 -declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8*, i32) #2 +declare void @llvm.arm.neon.vst4.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1 +declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0i8(i8*, i32) #2 ; Function Attrs: nounwind |
