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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2017-01-27 03:41:53 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2017-01-27 03:41:53 +0000 |
| commit | 26c00e3700078e021d8742ef6a18ac7736c434c9 (patch) | |
| tree | 139607deca8fcd314c38bceb7bd47fcda81246a2 /llvm/test/CodeGen/ARM/neon_div.ll | |
| parent | c479686af2542cf84a73a0a1ac4e637e1af34b8f (diff) | |
| download | bcm5719-llvm-26c00e3700078e021d8742ef6a18ac7736c434c9.tar.gz bcm5719-llvm-26c00e3700078e021d8742ef6a18ac7736c434c9.zip | |
ARM: fix vectorized division on WoA
The Windows on ARM target uses custom division for normal division as
the backend needs to insert division-by-zero checks. However, it is
designed to only handle non-vectorized division. ARM has custom
lowering for vectorized division as that can avoid loading registers
with the values and invoke a division routine for each one, preferring
to lower using NEON instructions. Fall back to the custom lowering for
the NEON instructions if we encounter a vectorized division.
Resolves PR31778!
llvm-svn: 293259
Diffstat (limited to 'llvm/test/CodeGen/ARM/neon_div.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/neon_div.ll | 83 |
1 files changed, 46 insertions, 37 deletions
diff --git a/llvm/test/CodeGen/ARM/neon_div.ll b/llvm/test/CodeGen/ARM/neon_div.ll index e185c2a8afb..23b626e0ce5 100644 --- a/llvm/test/CodeGen/ARM/neon_div.ll +++ b/llvm/test/CodeGen/ARM/neon_div.ll @@ -1,49 +1,58 @@ -; RUN: llc -mtriple=arm-eabi -mattr=+neon -pre-RA-sched=source -disable-post-ra %s -o - \ -; RUN: | FileCheck %s +; RUN: llc -mtriple arm-eabi -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s +; RUN: llc -mtriple thumbv7-windows-itanium -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrecpe.f32 -;CHECK: vmovn.i32 -;CHECK: vrecpe.f32 -;CHECK: vmovn.i32 -;CHECK: vmovn.i16 - %tmp1 = load <8 x i8>, <8 x i8>* %A - %tmp2 = load <8 x i8>, <8 x i8>* %B - %tmp3 = sdiv <8 x i8> %tmp1, %tmp2 - ret <8 x i8> %tmp3 + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = sdiv <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 } +; CHECK-LABEL: sdivi8: +; CHECK: vrecpe.f32 +; CHECK: vmovn.i32 +; CHECK: vrecpe.f32 +; CHECK: vmovn.i32 +; CHECK: vmovn.i16 + define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrecpe.f32 -;CHECK: vrecps.f32 -;CHECK: vmovn.i32 -;CHECK: vrecpe.f32 -;CHECK: vrecps.f32 -;CHECK: vmovn.i32 -;CHECK: vqmovun.s16 - %tmp1 = load <8 x i8>, <8 x i8>* %A - %tmp2 = load <8 x i8>, <8 x i8>* %B - %tmp3 = udiv <8 x i8> %tmp1, %tmp2 - ret <8 x i8> %tmp3 + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = udiv <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 } +; CHECK-LABEL: udivi8: +; CHECK: vrecpe.f32 +; CHECK: vrecps.f32 +; CHECK: vmovn.i32 +; CHECK: vrecpe.f32 +; CHECK: vrecps.f32 +; CHECK: vmovn.i32 +; CHECK: vqmovun.s16 + define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrecpe.f32 -;CHECK: vrecps.f32 -;CHECK: vmovn.i32 - %tmp1 = load <4 x i16>, <4 x i16>* %A - %tmp2 = load <4 x i16>, <4 x i16>* %B - %tmp3 = sdiv <4 x i16> %tmp1, %tmp2 - ret <4 x i16> %tmp3 + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = sdiv <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 } +; CHECK-LABEL: sdivi16: +; CHECK: vrecpe.f32 +; CHECK: vrecps.f32 +; CHECK: vmovn.i32 + define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrecpe.f32 -;CHECK: vrecps.f32 -;CHECK: vrecps.f32 -;CHECK: vmovn.i32 - %tmp1 = load <4 x i16>, <4 x i16>* %A - %tmp2 = load <4 x i16>, <4 x i16>* %B - %tmp3 = udiv <4 x i16> %tmp1, %tmp2 - ret <4 x i16> %tmp3 + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = udiv <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 } + +; CHECK-LABEL: udivi16: +; CHECK: vrecpe.f32 +; CHECK: vrecps.f32 +; CHECK: vrecps.f32 +; CHECK: vmovn.i32 + |
