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| author | Oliver Stannard <oliver.stannard@arm.com> | 2015-05-18 16:23:33 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2015-05-18 16:23:33 +0000 |
| commit | 0c553afe6a401d79f615faa5a72c991dc4654ec9 (patch) | |
| tree | 239128ff678a440117397a701a2989df1def2dbb /llvm/test/CodeGen/ARM/named-reg-alloc.ll | |
| parent | 45176c2341ef8e5efad9b765176fa9b69dfeb40a (diff) | |
| download | bcm5719-llvm-0c553afe6a401d79f615faa5a72c991dc4654ec9.tar.gz bcm5719-llvm-0c553afe6a401d79f615faa5a72c991dc4654ec9.zip | |
[LLVM - ARM/AArch64] Add ACLE special register intrinsics
This patch implements LLVM support for the ACLE special register intrinsics in
section 10.1, __arm_{w,r}sr{,p,64}.
This patch is intended to lower the read/write_register instrinsics, used to
implement the special register intrinsics in the clang patch for special
register intrinsics (see http://reviews.llvm.org/D9697), to ARM specific
instructions MRC,MCR,MSR etc. to allow reading an writing of coprocessor
registers in AArch32 and AArch64. This is done by inspecting the register
string passed to the intrinsic and then lowering to the appropriate
instruction.
Patch by Luke Cheeseman.
Differential Revision: http://reviews.llvm.org/D9699
llvm-svn: 237579
Diffstat (limited to 'llvm/test/CodeGen/ARM/named-reg-alloc.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/named-reg-alloc.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/named-reg-alloc.ll b/llvm/test/CodeGen/ARM/named-reg-alloc.ll index 380cf39734f..d41fa64882c 100644 --- a/llvm/test/CodeGen/ARM/named-reg-alloc.ll +++ b/llvm/test/CodeGen/ARM/named-reg-alloc.ll @@ -4,7 +4,7 @@ define i32 @get_stack() nounwind { entry: ; FIXME: Include an allocatable-specific error message -; CHECK: Invalid register name global variable +; CHECK: Invalid register name "r5". %sp = call i32 @llvm.read_register.i32(metadata !0) ret i32 %sp } |
