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| author | Tim Northover <tnorthover@apple.com> | 2017-04-20 19:54:02 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2017-04-20 19:54:02 +0000 |
| commit | 8b1240b0f09d53863cb298c7519508ddead3c957 (patch) | |
| tree | 1cac9a03fa15e5a1c881534db5a93e0cf571cdd3 /llvm/test/CodeGen/ARM/memset-inline.ll | |
| parent | 175d70ee5c2f03f640151488f5f33b7bd9b96f8d (diff) | |
| download | bcm5719-llvm-8b1240b0f09d53863cb298c7519508ddead3c957.tar.gz bcm5719-llvm-8b1240b0f09d53863cb298c7519508ddead3c957.zip | |
ARM: handle post-indexed NEON ops where the offset isn't the access width.
Before, we assumed that any ConstantInt offset was precisely the access width,
so we could use the "[rN]!" form. ISelLowering only ever created that kind, but
further simplification during combining could lead to unexpected constants and
incorrect codegen.
Should fix PR32658.
llvm-svn: 300878
Diffstat (limited to 'llvm/test/CodeGen/ARM/memset-inline.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/memset-inline.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/memset-inline.ll b/llvm/test/CodeGen/ARM/memset-inline.ll index f6f8d562350..b86874692ac 100644 --- a/llvm/test/CodeGen/ARM/memset-inline.ll +++ b/llvm/test/CodeGen/ARM/memset-inline.ll @@ -13,10 +13,10 @@ entry: define void @t2() nounwind ssp { entry: ; CHECK-LABEL: t2: -; CHECK: add.w r1, r0, #10 ; CHECK: vmov.i32 {{q[0-9]+}}, #0x0 -; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] -; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] +; CHECK: movs r1, #10 +; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1 +; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2] %buf = alloca [26 x i8], align 1 %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false) |
