diff options
| author | Andrew Trick <atrick@apple.com> | 2011-04-12 19:54:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-04-12 19:54:36 +0000 |
| commit | c5dd24a54215f06cb8b1320d0ca2b85ac334a25e (patch) | |
| tree | a2ed15ecd7de38846a9451ab06b9e92b56f55a1b /llvm/test/CodeGen/ARM/memcpy-inline.ll | |
| parent | 23fe31cc8d50b023cfd3f6fc79388f864eb48311 (diff) | |
| download | bcm5719-llvm-c5dd24a54215f06cb8b1320d0ca2b85ac334a25e.tar.gz bcm5719-llvm-c5dd24a54215f06cb8b1320d0ca2b85ac334a25e.zip | |
PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make these heuristic adjustments to node latency work,
I also needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
llvm-svn: 129383
Diffstat (limited to 'llvm/test/CodeGen/ARM/memcpy-inline.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/memcpy-inline.ll | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/ARM/memcpy-inline.ll b/llvm/test/CodeGen/ARM/memcpy-inline.ll index e8a2a3b7d5b..5bae037cafb 100644 --- a/llvm/test/CodeGen/ARM/memcpy-inline.ll +++ b/llvm/test/CodeGen/ARM/memcpy-inline.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s ; The ARM magic hinting works best with linear scan. -; CHECK: ldmia -; CHECK: stmia -; CHECK: ldrh +; CHECK: ldrd +; CHECK: strd ; CHECK: ldrb %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } |
