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author | Andrew Trick <atrick@apple.com> | 2011-04-13 00:38:32 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2011-04-13 00:38:32 +0000 |
commit | b53a00d2cbc643d461ebd57e8f029f38631bfd34 (patch) | |
tree | 0bb4300556bfe91933aaf65004de971f1ac5d721 /llvm/test/CodeGen/ARM/memcpy-inline.ll | |
parent | 3137d3cb499af07c021f5a12dad1cd5418dd024f (diff) | |
download | bcm5719-llvm-b53a00d2cbc643d461ebd57e8f029f38631bfd34.tar.gz bcm5719-llvm-b53a00d2cbc643d461ebd57e8f029f38631bfd34.zip |
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.
Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
llvm-svn: 129421
Diffstat (limited to 'llvm/test/CodeGen/ARM/memcpy-inline.ll')
-rw-r--r-- | llvm/test/CodeGen/ARM/memcpy-inline.ll | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/ARM/memcpy-inline.ll b/llvm/test/CodeGen/ARM/memcpy-inline.ll index e8a2a3b7d5b..5bae037cafb 100644 --- a/llvm/test/CodeGen/ARM/memcpy-inline.ll +++ b/llvm/test/CodeGen/ARM/memcpy-inline.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s ; The ARM magic hinting works best with linear scan. -; CHECK: ldmia -; CHECK: stmia -; CHECK: ldrh +; CHECK: ldrd +; CHECK: strd ; CHECK: ldrb %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } |