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| author | Tim Northover <tnorthover@apple.com> | 2016-05-13 19:16:14 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-05-13 19:16:14 +0000 |
| commit | f8b0a7af52f8c4ec6b4ddcfe3a6fa75098c9507c (patch) | |
| tree | 2219a9d046854c8652752a7a5734652c31b13ebf /llvm/test/CodeGen/ARM/macho-frame-offset.ll | |
| parent | 0f791f44c72bc5b52dfb31bcf6b6fe4f411d5fd2 (diff) | |
| download | bcm5719-llvm-f8b0a7af52f8c4ec6b4ddcfe3a6fa75098c9507c.tar.gz bcm5719-llvm-f8b0a7af52f8c4ec6b4ddcfe3a6fa75098c9507c.zip | |
ARM: use callee-saved list in the order they're actually saved.
When setting the frame pointer, the offset from SP is calculated based on the
stack slot it gets allocated, but this slot is in turn based on the order of
the CSR list so that list should match the order we actually save the registers
in. Mostly it did, but in the edge-case of MachO AAPCS targets it was wrong.
llvm-svn: 269459
Diffstat (limited to 'llvm/test/CodeGen/ARM/macho-frame-offset.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/macho-frame-offset.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/macho-frame-offset.ll b/llvm/test/CodeGen/ARM/macho-frame-offset.ll new file mode 100644 index 00000000000..f3dacf66b6c --- /dev/null +++ b/llvm/test/CodeGen/ARM/macho-frame-offset.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple thumbv7m-apple-macho -disable-fp-elim -o - %s | FileCheck %s + +define void @func() { +; CHECK-LABEL: func: +; CHECK: push {r6, r7, lr} +; CHECK: add r7, sp, #4 + call void @bar() + call void asm sideeffect "", "~{r11}"() + ret void +} + +declare void @bar() |
