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| author | Evan Cheng <evan.cheng@apple.com> | 2010-11-12 20:32:20 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-11-12 20:32:20 +0000 |
| commit | 2d59ee34f11f63067c8ba6c1f894dfc6eddd802c (patch) | |
| tree | 1edbfdd7fb4f2fddde96afc1cfd9fc18e77f5e23 /llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll | |
| parent | 6bb1ae9d45e1cff18273092ab320ea9dd51ee83e (diff) | |
| download | bcm5719-llvm-2d59ee34f11f63067c8ba6c1f894dfc6eddd802c.tar.gz bcm5719-llvm-2d59ee34f11f63067c8ba6c1f894dfc6eddd802c.zip | |
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
llvm-svn: 118922
Diffstat (limited to 'llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 52e40b234ba..9882690da26 100644 --- a/llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/llvm/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -4,14 +4,14 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s{{.*}}, [lr, #-128] -; CHECK: vstr.32 s{{.*}}, [lr, #-96] -; CHECK: vstr.32 s{{.*}}, [lr, #-64] -; CHECK: vstr.32 s{{.*}}, [lr, #-32] -; CHECK: vstr.32 s{{.*}}, [lr] -; CHECK: vstr.32 s{{.*}}, [lr, #32] -; CHECK: vstr.32 s{{.*}}, [lr, #64] -; CHECK: vstr.32 s{{.*}}, [lr, #96] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-128] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-96] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-64] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-32] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96] target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -627,7 +627,7 @@ bb24: ; preds = %bb23 ; in a register. ; CHECK: @ %bb24 -; CHECK: subs{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1 +; CHECK: subs{{.*}} {{(r[0-9]+)|(lr)}}, #1 ; CHECK: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1] |
