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| author | Eugene Leviant <eleviant@accesssoftek.com> | 2017-11-21 11:01:28 +0000 |
|---|---|---|
| committer | Eugene Leviant <eleviant@accesssoftek.com> | 2017-11-21 11:01:28 +0000 |
| commit | 6bc35a93e6be166ec25cc42ab081ea161740ba3b (patch) | |
| tree | dd47eed5f215d3bf5f551553d3e940621c9dd306 /llvm/test/CodeGen/ARM/load-global2.ll | |
| parent | 5c7fe5df5312d02c027531a9121e7ac9e8e01b73 (diff) | |
| download | bcm5719-llvm-6bc35a93e6be166ec25cc42ab081ea161740ba3b.tar.gz bcm5719-llvm-6bc35a93e6be166ec25cc42ab081ea161740ba3b.zip | |
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
This patch fixes instregex for interger vector add/sub instructions
Differential revision: https://reviews.llvm.org/D40254
llvm-svn: 318749
Diffstat (limited to 'llvm/test/CodeGen/ARM/load-global2.ll')
0 files changed, 0 insertions, 0 deletions
