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| author | Artur Pilipenko <apilipenko@azulsystems.com> | 2017-02-16 17:07:27 +0000 |
|---|---|---|
| committer | Artur Pilipenko <apilipenko@azulsystems.com> | 2017-02-16 17:07:27 +0000 |
| commit | 85d758299e480ad4b0c924a971dc79b7809b5acd (patch) | |
| tree | c5ab9abb102ca868cfdf05c0af50668d2bad780d /llvm/test/CodeGen/ARM/load-combine.ll | |
| parent | fc711b1f4772dd14ce679176e499683ee7c8642f (diff) | |
| download | bcm5719-llvm-85d758299e480ad4b0c924a971dc79b7809b5acd.tar.gz bcm5719-llvm-85d758299e480ad4b0c924a971dc79b7809b5acd.zip | |
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine
Resubmit -r295314 with PowerPC and AMDGPU tests updated.
Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters.
Reviewed By: filcab
Differential Revision: https://reviews.llvm.org/D29591
llvm-svn: 295336
Diffstat (limited to 'llvm/test/CodeGen/ARM/load-combine.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/load-combine.ll | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll index f19911a8e66..720bc7b88b3 100644 --- a/llvm/test/CodeGen/ARM/load-combine.ll +++ b/llvm/test/CodeGen/ARM/load-combine.ll @@ -414,17 +414,12 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) { ; (i32) p[0] | (sext(p[1] << 16) to i32) define i32 @load_i32_by_sext_i16(i32* %arg) { ; CHECK-LABEL: load_i32_by_sext_i16: -; CHECK: ldrh r1, [r0, #2] -; CHECK-NEXT: ldrh r0, [r0] -; CHECK-NEXT: orr r0, r0, r1, lsl #16 +; CHECK: ldr r0, [r0] ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_sext_i16: -; CHECK-ARMv6: ldrh r1, [r0, #2] -; CHECK-ARMv6-NEXT: ldrh r0, [r0] -; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #16 -; CHECK-ARMv6-NEXT: bx lr - +; CHECK-ARMv6: ldr r0, [r0] +; CHECK-ARMv6-NEXT: bx lr %tmp = bitcast i32* %arg to i16* %tmp1 = load i16, i16* %tmp, align 4 %tmp2 = zext i16 %tmp1 to i32 @@ -492,7 +487,6 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) { ; CHECK-ARMv6: add r0, r0, r1 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13] ; CHECK-ARMv6-NEXT: bx lr - %tmp = add nuw nsw i32 %i, 4 %tmp2 = add nuw nsw i32 %i, 3 %tmp3 = add nuw nsw i32 %i, 2 |
