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| author | Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> | 2019-04-29 17:50:10 +0000 |
|---|---|---|
| committer | Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> | 2019-04-29 17:50:10 +0000 |
| commit | 820994572c636c5817488f7e9ef5074b0b2a7ed0 (patch) | |
| tree | 7636e4473daae26056006cd3f3c835b89846de75 /llvm/test/CodeGen/ARM/load-combine.ll | |
| parent | 15cb1f1501047ac4fb4ae142a9b4570a3cb74741 (diff) | |
| download | bcm5719-llvm-820994572c636c5817488f7e9ef5074b0b2a7ed0.tar.gz bcm5719-llvm-820994572c636c5817488f7e9ef5074b0b2a7ed0.zip | |
[DAG] Refactor DAGCombiner::ReassociateOps
Summary:
Extract the logic for doing reassociations
from DAGCombiner::reassociateOps into a helper
function DAGCombiner::reassociateOpsCommutative,
and use that helper to trigger reassociation
on the original operand order, or the commuted
operand order.
Codegen is not identical since the operand order will
be different when doing the reassociations for the
commuted case. That causes some unfortunate churn in
some test cases. Apart from that this should be NFC.
Reviewers: spatel, craig.topper, tstellar
Reviewed By: spatel
Subscribers: dmgreen, dschuff, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, hiraditya, aheejin, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61199
llvm-svn: 359476
Diffstat (limited to 'llvm/test/CodeGen/ARM/load-combine.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/load-combine.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll index 72f4c5c7419..4206aad1d9e 100644 --- a/llvm/test/CodeGen/ARM/load-combine.ll +++ b/llvm/test/CodeGen/ARM/load-combine.ll @@ -479,12 +479,12 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) { ; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24) define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) { ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2: -; CHECK: add r0, r0, r1 +; CHECK: add r0, r1, r0 ; CHECK-NEXT: ldr r0, [r0, #13] ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2: -; CHECK-ARMv6: add r0, r0, r1 +; CHECK-ARMv6: add r0, r1, r0 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13] ; CHECK-ARMv6-NEXT: bx lr %tmp = add nuw nsw i32 %i, 4 |
